From: "José Roberto de Souza" <jose.souza@intel.com> To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/5] drm/i915/display: Handle fused off HDCP Date: Fri, 25 Oct 2019 17:13:20 -0700 [thread overview] Message-ID: <20191026001323.216052-2-jose.souza@intel.com> (raw) In-Reply-To: <20191026001323.216052-1-jose.souza@intel.com> HDCP could be fused off, so not all GEN9+ platforms will support it. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Martin Peres <martin.peres@linux.intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_device_info.c | 3 +++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 5 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index e69fa34528df..f1f41ca8402b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work) bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) { /* PORT E doesn't have HDCP, and PORT F is disabled */ - return INTEL_GEN(dev_priv) >= 9 && port < PORT_E; + return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E; } static int diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 04307e111f57..430da2d4082a 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_logical_ring_preemption = 1, \ .display.has_csr = 1, \ .has_gt_uc = 1, \ + .display.has_hdcp = 1, \ .display.has_ipc = 1, \ .ddb_size = 896 @@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { .display.has_ddi = 1, \ .has_fpga_dbg = 1, \ .display.has_fbc = 1, \ + .display.has_hdcp = 1, \ .display.has_psr = 1, \ .has_runtime_pm = 1, \ .display.has_csr = 1, \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09cb43f4e976..1317c0df76b7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7663,6 +7663,7 @@ enum { #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) #define SKL_DFSM _MMIO(0x51000) +#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 85e480bdc673..e7dd6092c105 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -981,6 +981,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) enabled_mask); else info->pipe_mask = enabled_mask; + + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) + info->display.has_hdcp = 0; } /* Initialize slice/subslice/EU info */ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 78a383f63957..64e4f1923c68 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -139,6 +139,7 @@ enum intel_ppgtt_type { func(has_dsb); \ func(has_fbc); \ func(has_gmch); \ + func(has_hdcp); \ func(has_hotplug); \ func(has_ipc); \ func(has_modular_fia); \ -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: "José Roberto de Souza" <jose.souza@intel.com> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 2/5] drm/i915/display: Handle fused off HDCP Date: Fri, 25 Oct 2019 17:13:20 -0700 [thread overview] Message-ID: <20191026001323.216052-2-jose.souza@intel.com> (raw) Message-ID: <20191026001320.z7ez8utU5rQq1fC-R7ZBm4Uh9S1WPJqQs65OZ1o-S0s@z> (raw) In-Reply-To: <20191026001323.216052-1-jose.souza@intel.com> HDCP could be fused off, so not all GEN9+ platforms will support it. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Martin Peres <martin.peres@linux.intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_device_info.c | 3 +++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 5 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index e69fa34528df..f1f41ca8402b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work) bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) { /* PORT E doesn't have HDCP, and PORT F is disabled */ - return INTEL_GEN(dev_priv) >= 9 && port < PORT_E; + return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E; } static int diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 04307e111f57..430da2d4082a 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_logical_ring_preemption = 1, \ .display.has_csr = 1, \ .has_gt_uc = 1, \ + .display.has_hdcp = 1, \ .display.has_ipc = 1, \ .ddb_size = 896 @@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { .display.has_ddi = 1, \ .has_fpga_dbg = 1, \ .display.has_fbc = 1, \ + .display.has_hdcp = 1, \ .display.has_psr = 1, \ .has_runtime_pm = 1, \ .display.has_csr = 1, \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09cb43f4e976..1317c0df76b7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7663,6 +7663,7 @@ enum { #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) #define SKL_DFSM _MMIO(0x51000) +#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 85e480bdc673..e7dd6092c105 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -981,6 +981,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) enabled_mask); else info->pipe_mask = enabled_mask; + + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) + info->display.has_hdcp = 0; } /* Initialize slice/subslice/EU info */ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 78a383f63957..64e4f1923c68 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -139,6 +139,7 @@ enum intel_ppgtt_type { func(has_dsb); \ func(has_fbc); \ func(has_gmch); \ + func(has_hdcp); \ func(has_hotplug); \ func(has_ipc); \ func(has_modular_fia); \ -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-10-26 0:14 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-26 0:13 [PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers José Roberto de Souza 2019-10-26 0:13 ` [Intel-gfx] " José Roberto de Souza 2019-10-26 0:13 ` José Roberto de Souza [this message] 2019-10-26 0:13 ` [Intel-gfx] [PATCH 2/5] drm/i915/display: Handle fused off HDCP José Roberto de Souza 2019-10-26 0:13 ` [PATCH 3/5] drm/i915/display: Check if FBC is fused off José Roberto de Souza 2019-10-26 0:13 ` [Intel-gfx] " José Roberto de Souza 2019-10-26 0:13 ` [PATCH 4/5] drm/i915/display/icl+: Check if DMC " José Roberto de Souza 2019-10-26 0:13 ` [Intel-gfx] " José Roberto de Souza 2019-10-26 0:13 ` [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC José Roberto de Souza 2019-10-26 0:13 ` [Intel-gfx] " José Roberto de Souza 2019-10-26 2:04 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Add two spaces before the SKL_DFSM registers Patchwork 2019-10-26 2:04 ` [Intel-gfx] " Patchwork 2019-10-27 20:42 ` ✓ Fi.CI.IGT: " Patchwork 2019-10-27 20:42 ` [Intel-gfx] " Patchwork 2019-10-29 19:36 ` Souza, Jose 2019-10-29 19:36 ` [Intel-gfx] " Souza, Jose 2019-10-29 18:24 ` [PATCH 1/5] " Radhakrishna Sripada 2019-10-29 18:24 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-01 4:44 ` Ramalingam C 2019-11-01 4:44 ` [Intel-gfx] " Ramalingam C -- strict thread matches above, loose matches on Subject: below -- 2019-10-19 0:41 [PATCH 1/5] drm/i915/display: Handle fused off display correctly José Roberto de Souza 2019-10-19 0:41 ` [PATCH 2/5] drm/i915/display: Handle fused off HDCP José Roberto de Souza 2019-10-23 13:37 ` Ramalingam C 2019-10-23 18:54 ` Souza, Jose 2019-10-24 6:57 ` Ramalingam C
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