From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, fisher.cheng@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Subject: [PATCH v6 0/7] Add Bitmain BM1880 clock driver Date: Sat, 26 Oct 2019 16:32:46 +0530 [thread overview] Message-ID: <20191026110253.18426-1-manivannan.sadhasivam@linaro.org> (raw) Hello, This patchset adds common clock driver for Bitmain BM1880 SoC clock controller. The clock controller consists of gate, divider, mux and pll clocks with different compositions. Hence, the driver uses composite clock structure in place where multiple clocking units are combined together. This patchset also removes UART fixed clock and sources clocks from clock controller for Sophon Edge board where the driver has been validated. Thanks, Mani Changes in v6: * Dropped 'clk: Warn if clk_init_data is not zero initialized' patch * Added fixes tag to the patch adding 'clk_hw_unregister_composite' definition * Reworked the use of CLK_IS_CTITICAL flag from clk driver * Removed the use of CLK_DIVIDER_HIWORD_MASK flag from driver * Some misc cleanups to the driver * Added Rob's reviewed tag for the binding Changes in v5: * Incorporated review comments from Rob on dt binding Changes in v4: * Fixed devicetree binding issue * Added ARCH_BITMAIN as the default for the clk driver Changes in v3: * Switched to clk_hw_{register/unregister} APIs * Returned clk_hw from the in-driver registration helpers Changes in v2: * Converted the dt binding to YAML * Incorporated review comments from Stephen (majority of change is switching to new way of specifying clk parents) Manivannan Sadhasivam (7): clk: Zero init clk_init_data in helpers clk: Add clk_hw_unregister_composite helper function definition dt-bindings: clock: Add devicetree binding for BM1880 SoC arm64: dts: bitmain: Add clock controller support for BM1880 SoC arm64: dts: bitmain: Source common clock for UART controllers clk: Add common clock driver for BM1880 SoC MAINTAINERS: Add entry for BM1880 SoC clock driver .../bindings/clock/bitmain,bm1880-clk.yaml | 76 ++ MAINTAINERS | 2 + .../boot/dts/bitmain/bm1880-sophon-edge.dts | 9 - arch/arm64/boot/dts/bitmain/bm1880.dtsi | 28 + drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-bm1880.c | 970 ++++++++++++++++++ drivers/clk/clk-composite.c | 13 +- drivers/clk/clk-divider.c | 2 +- drivers/clk/clk-fixed-rate.c | 2 +- drivers/clk/clk-gate.c | 2 +- drivers/clk/clk-mux.c | 2 +- include/dt-bindings/clock/bm1880-clock.h | 82 ++ 13 files changed, 1182 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml create mode 100644 drivers/clk/clk-bm1880.c create mode 100644 include/dt-bindings/clock/bm1880-clock.h -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, darren.tsao@bitmain.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, fisher.cheng@bitmain.com, alec.lin@bitmain.com, linux-clk@vger.kernel.org, haitao.suo@bitmain.com Subject: [PATCH v6 0/7] Add Bitmain BM1880 clock driver Date: Sat, 26 Oct 2019 16:32:46 +0530 [thread overview] Message-ID: <20191026110253.18426-1-manivannan.sadhasivam@linaro.org> (raw) Hello, This patchset adds common clock driver for Bitmain BM1880 SoC clock controller. The clock controller consists of gate, divider, mux and pll clocks with different compositions. Hence, the driver uses composite clock structure in place where multiple clocking units are combined together. This patchset also removes UART fixed clock and sources clocks from clock controller for Sophon Edge board where the driver has been validated. Thanks, Mani Changes in v6: * Dropped 'clk: Warn if clk_init_data is not zero initialized' patch * Added fixes tag to the patch adding 'clk_hw_unregister_composite' definition * Reworked the use of CLK_IS_CTITICAL flag from clk driver * Removed the use of CLK_DIVIDER_HIWORD_MASK flag from driver * Some misc cleanups to the driver * Added Rob's reviewed tag for the binding Changes in v5: * Incorporated review comments from Rob on dt binding Changes in v4: * Fixed devicetree binding issue * Added ARCH_BITMAIN as the default for the clk driver Changes in v3: * Switched to clk_hw_{register/unregister} APIs * Returned clk_hw from the in-driver registration helpers Changes in v2: * Converted the dt binding to YAML * Incorporated review comments from Stephen (majority of change is switching to new way of specifying clk parents) Manivannan Sadhasivam (7): clk: Zero init clk_init_data in helpers clk: Add clk_hw_unregister_composite helper function definition dt-bindings: clock: Add devicetree binding for BM1880 SoC arm64: dts: bitmain: Add clock controller support for BM1880 SoC arm64: dts: bitmain: Source common clock for UART controllers clk: Add common clock driver for BM1880 SoC MAINTAINERS: Add entry for BM1880 SoC clock driver .../bindings/clock/bitmain,bm1880-clk.yaml | 76 ++ MAINTAINERS | 2 + .../boot/dts/bitmain/bm1880-sophon-edge.dts | 9 - arch/arm64/boot/dts/bitmain/bm1880.dtsi | 28 + drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-bm1880.c | 970 ++++++++++++++++++ drivers/clk/clk-composite.c | 13 +- drivers/clk/clk-divider.c | 2 +- drivers/clk/clk-fixed-rate.c | 2 +- drivers/clk/clk-gate.c | 2 +- drivers/clk/clk-mux.c | 2 +- include/dt-bindings/clock/bm1880-clock.h | 82 ++ 13 files changed, 1182 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml create mode 100644 drivers/clk/clk-bm1880.c create mode 100644 include/dt-bindings/clock/bm1880-clock.h -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2019-10-26 11:03 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-26 11:02 Manivannan Sadhasivam [this message] 2019-10-26 11:02 ` [PATCH v6 0/7] Add Bitmain BM1880 clock driver Manivannan Sadhasivam 2019-10-26 11:02 ` [PATCH v6 1/7] clk: Zero init clk_init_data in helpers Manivannan Sadhasivam 2019-10-26 11:02 ` Manivannan Sadhasivam 2019-10-26 11:02 ` [PATCH v6 2/7] clk: Add clk_hw_unregister_composite helper function definition Manivannan Sadhasivam 2019-10-26 11:02 ` Manivannan Sadhasivam 2019-10-26 11:02 ` [PATCH v6 3/7] dt-bindings: clock: Add devicetree binding for BM1880 SoC Manivannan Sadhasivam 2019-10-26 11:02 ` Manivannan Sadhasivam 2019-10-26 11:02 ` [PATCH v6 4/7] arm64: dts: bitmain: Add clock controller support " Manivannan Sadhasivam 2019-10-26 11:02 ` Manivannan Sadhasivam 2019-10-26 11:02 ` [PATCH v6 5/7] arm64: dts: bitmain: Source common clock for UART controllers Manivannan Sadhasivam 2019-10-26 11:02 ` Manivannan Sadhasivam 2019-10-26 11:02 ` [PATCH v6 6/7] clk: Add common clock driver for BM1880 SoC Manivannan Sadhasivam 2019-10-26 11:02 ` Manivannan Sadhasivam 2019-10-29 9:01 ` kbuild test robot 2019-10-29 9:01 ` kbuild test robot 2019-10-29 9:01 ` kbuild test robot 2019-10-30 3:44 ` kbuild test robot 2019-10-30 3:44 ` kbuild test robot 2019-10-26 11:02 ` [PATCH v6 7/7] MAINTAINERS: Add entry for BM1880 SoC clock driver Manivannan Sadhasivam 2019-10-26 11:02 ` Manivannan Sadhasivam 2019-11-13 22:21 ` [PATCH v6 0/7] Add Bitmain BM1880 " Stephen Boyd 2019-11-13 22:21 ` Stephen Boyd 2019-11-14 5:34 ` Manivannan Sadhasivam 2019-11-14 5:34 ` Manivannan Sadhasivam 2019-11-14 5:50 ` Stephen Boyd 2019-11-14 5:50 ` Stephen Boyd 2019-11-14 6:09 ` Manivannan Sadhasivam 2019-11-14 6:09 ` Manivannan Sadhasivam
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