From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [CI] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency Date: Mon, 28 Oct 2019 20:30:12 +0000 [thread overview] Message-ID: <20191028203012.14566-1-chris@chris-wilson.co.uk> (raw) Currently we insert a arbitration point every 128MiB during a blitter copy. At 8GiB/s, this is around 30ms. This is a little on the large side if we need to inject a high priority work, so reduced it down to 8MiB or roughly 1ms. v2: Don't forget both fill/copy. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index 516e61e99212..51acffd31575 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, u32 value) { struct drm_i915_private *i915 = ce->vm->i915; - const u32 block_size = S16_MAX * PAGE_SIZE; + const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */ struct intel_engine_pool_node *pool; struct i915_vma *batch; u64 offset; @@ -201,7 +201,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, struct i915_vma *dst) { struct drm_i915_private *i915 = ce->vm->i915; - const u32 block_size = S16_MAX * PAGE_SIZE; + const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */ struct intel_engine_pool_node *pool; struct i915_vma *batch; u64 src_offset, dst_offset; -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [CI] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency Date: Mon, 28 Oct 2019 20:30:12 +0000 [thread overview] Message-ID: <20191028203012.14566-1-chris@chris-wilson.co.uk> (raw) Message-ID: <20191028203012.63mL1lJFDUKUIsvZgO3IfysBMOv5ilraNYll1XSZJds@z> (raw) Currently we insert a arbitration point every 128MiB during a blitter copy. At 8GiB/s, this is around 30ms. This is a little on the large side if we need to inject a high priority work, so reduced it down to 8MiB or roughly 1ms. v2: Don't forget both fill/copy. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index 516e61e99212..51acffd31575 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, u32 value) { struct drm_i915_private *i915 = ce->vm->i915; - const u32 block_size = S16_MAX * PAGE_SIZE; + const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */ struct intel_engine_pool_node *pool; struct i915_vma *batch; u64 offset; @@ -201,7 +201,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, struct i915_vma *dst) { struct drm_i915_private *i915 = ce->vm->i915; - const u32 block_size = S16_MAX * PAGE_SIZE; + const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */ struct intel_engine_pool_node *pool; struct i915_vma *batch; u64 src_offset, dst_offset; -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2019-10-28 20:30 UTC|newest] Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-28 20:30 Chris Wilson [this message] 2019-10-28 20:30 ` [Intel-gfx] [CI] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency Chris Wilson 2019-10-28 23:56 ` ✗ Fi.CI.BAT: failure for drm/i915/gem: Limit the blitter sizes to ensure low preemption latency (rev2) Patchwork 2019-10-28 23:56 ` [Intel-gfx] " Patchwork
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