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From: <mikita.lipski-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: David Francis <David.Francis-5C7GfCeVMHo@public.gmane.org>,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH 08/13] drm/amd/display: Initialize DSC PPS variables to 0
Date: Tue, 29 Oct 2019 09:52:40 -0400	[thread overview]
Message-ID: <20191029135245.31152-9-mikita.lipski@amd.com> (raw)
In-Reply-To: <20191029135245.31152-1-mikita.lipski-5C7GfCeVMHo@public.gmane.org>

From: David Francis <David.Francis@amd.com>

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index a519dbc5ecb6..5d6cbaebebc0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -496,6 +496,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
 		struct dsc_config dsc_cfg;
 		uint8_t dsc_packed_pps[128];
 
+		memset(&dsc_cfg, 0, sizeof(dsc_cfg));
+		memset(dsc_packed_pps, 0, 128);
+
 		/* Enable DSC hw block */
 		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 63eb377ed9c0..296eeff00296 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
 	struct dsc_reg_values dsc_reg_vals;
 	struct dsc_optc_config dsc_optc_cfg;
 
+	memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
+	memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
 	DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
 	dsc_config_log(dsc, dsc_cfg);
 	DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

WARNING: multiple messages have this Message-ID (diff)
From: <mikita.lipski@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: David Francis <David.Francis@amd.com>, dri-devel@lists.freedesktop.org
Subject: [PATCH 08/13] drm/amd/display: Initialize DSC PPS variables to 0
Date: Tue, 29 Oct 2019 09:52:40 -0400	[thread overview]
Message-ID: <20191029135245.31152-9-mikita.lipski@amd.com> (raw)
Message-ID: <20191029135240.lO1Cb59Sol-_nkn806hkc5OYpj0x8uzUgKJfIorOdtg@z> (raw)
In-Reply-To: <20191029135245.31152-1-mikita.lipski@amd.com>

From: David Francis <David.Francis@amd.com>

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index a519dbc5ecb6..5d6cbaebebc0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -496,6 +496,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
 		struct dsc_config dsc_cfg;
 		uint8_t dsc_packed_pps[128];
 
+		memset(&dsc_cfg, 0, sizeof(dsc_cfg));
+		memset(dsc_packed_pps, 0, 128);
+
 		/* Enable DSC hw block */
 		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 63eb377ed9c0..296eeff00296 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
 	struct dsc_reg_values dsc_reg_vals;
 	struct dsc_optc_config dsc_optc_cfg;
 
+	memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
+	memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
 	DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
 	dsc_config_log(dsc, dsc_cfg);
 	DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: <mikita.lipski@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: David Francis <David.Francis@amd.com>, dri-devel@lists.freedesktop.org
Subject: [PATCH 08/13] drm/amd/display: Initialize DSC PPS variables to 0
Date: Tue, 29 Oct 2019 09:52:40 -0400	[thread overview]
Message-ID: <20191029135245.31152-9-mikita.lipski@amd.com> (raw)
Message-ID: <20191029135240.HM1AfRbxhEKarbJx1YO_lGlY0L_ZVYJKuOpb4MHr5uc@z> (raw)
In-Reply-To: <20191029135245.31152-1-mikita.lipski@amd.com>

From: David Francis <David.Francis@amd.com>

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index a519dbc5ecb6..5d6cbaebebc0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -496,6 +496,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
 		struct dsc_config dsc_cfg;
 		uint8_t dsc_packed_pps[128];
 
+		memset(&dsc_cfg, 0, sizeof(dsc_cfg));
+		memset(dsc_packed_pps, 0, 128);
+
 		/* Enable DSC hw block */
 		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 63eb377ed9c0..296eeff00296 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
 	struct dsc_reg_values dsc_reg_vals;
 	struct dsc_optc_config dsc_optc_cfg;
 
+	memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
+	memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
 	DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
 	dsc_config_log(dsc, dsc_cfg);
 	DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2019-10-29 13:52 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-29 13:52 [PATCH v3 00/13] DSC MST support for AMDGPU mikita.lipski-5C7GfCeVMHo
2019-10-29 13:52 ` mikita.lipski
2019-10-29 13:52 ` mikita.lipski
2019-10-29 13:52 ` [PATCH 02/13] drm/dp_mst: Add PBN calculation for DSC modes mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52 ` [PATCH 04/13] drm/dp_mst: Add MST support to DP DPCD R/W functions mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52 ` [PATCH 05/13] drm/dp_mst: Fill branch->num_ports mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52 ` [PATCH 07/13] drm/dp_mst: Add new quirk for Synaptics MST hubs mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52 ` [PATCH 11/13] drm/amd/display: MST DSC compute fair share mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52   ` mikita.lipski
     [not found] ` <20191029135245.31152-1-mikita.lipski-5C7GfCeVMHo@public.gmane.org>
2019-10-29 13:52   ` [PATCH 01/13] drm/amd/display: Add MST atomic routines mikita.lipski-5C7GfCeVMHo
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52   ` [PATCH 03/13] drm/dp_mst: Parse FEC capability on MST ports mikita.lipski-5C7GfCeVMHo
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52   ` [PATCH 06/13] drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux mikita.lipski-5C7GfCeVMHo
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52   ` mikita.lipski-5C7GfCeVMHo [this message]
2019-10-29 13:52     ` [PATCH 08/13] drm/amd/display: Initialize DSC PPS variables to 0 mikita.lipski
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52   ` [PATCH 09/13] drm/amd/display: Validate DSC caps on MST endpoints mikita.lipski-5C7GfCeVMHo
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52   ` [PATCH 10/13] drm/amd/display: Write DSC enable to MST DPCD mikita.lipski-5C7GfCeVMHo
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52   ` [PATCH 12/13] drm/dp_mst: Add DSC enablement helpers to DRM mikita.lipski-5C7GfCeVMHo
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52     ` mikita.lipski
2019-10-29 13:52 ` [PATCH 13/13] drm/amd/display: Recalculate VCPI slots for new DSC connectors mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-29 13:52   ` mikita.lipski
2019-10-30 19:24 [PATCH v4 00/13] DSC MST support for AMDGPU mikita.lipski-5C7GfCeVMHo
     [not found] ` <20191030192431.5798-1-mikita.lipski-5C7GfCeVMHo@public.gmane.org>
2019-10-30 19:24   ` [PATCH 08/13] drm/amd/display: Initialize DSC PPS variables to 0 mikita.lipski-5C7GfCeVMHo
2019-10-30 19:24     ` mikita.lipski
2019-10-30 19:24     ` mikita.lipski

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