All of lore.kernel.org
 help / color / mirror / Atom feed
From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/5] drm/i915/psr: Check if sink PSR capability changed
Date: Tue,  5 Nov 2019 17:45:03 -0800	[thread overview]
Message-ID: <20191106014504.167656-4-jose.souza@intel.com> (raw)
In-Reply-To: <20191106014504.167656-1-jose.souza@intel.com>

eDP specification states that sink can have its PSR capability
changed, I have never found any panel doing that but lets add that
for completeness.
For now it is not reading back the PSR capabilities and if possible
re-enabling PSR, this will be added if a panel is found using this
feature.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c703a10d2fd7..cdd9c270b42c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1437,6 +1437,26 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
 	}
 }
 
+static void psr_capability_changed_check(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct i915_psr *psr = &dev_priv->psr;
+	u8 val;
+	int r;
+
+	r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
+	if (r != 1) {
+		DRM_ERROR("Error reading DP_PSR_ESI\n");
+		return;
+	}
+
+	if (val & DP_PSR_CAPS_CHANGE) {
+		intel_psr_disable_locked(intel_dp);
+		psr->sink_not_reliable = true;
+		DRM_DEBUG_KMS("Sink PSR capability changed, disabling PSR\n");
+	}
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1480,6 +1500,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
 
 	psr_alpm_check(intel_dp);
+	psr_capability_changed_check(intel_dp);
 
 exit:
 	mutex_unlock(&psr->lock);
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 4/5] drm/i915/psr: Check if sink PSR capability changed
Date: Tue,  5 Nov 2019 17:45:03 -0800	[thread overview]
Message-ID: <20191106014504.167656-4-jose.souza@intel.com> (raw)
Message-ID: <20191106014503.yOD25sZEgFl4KSeCyB1kCe7dWPxgH0hEX1wqpjbTzNk@z> (raw)
In-Reply-To: <20191106014504.167656-1-jose.souza@intel.com>

eDP specification states that sink can have its PSR capability
changed, I have never found any panel doing that but lets add that
for completeness.
For now it is not reading back the PSR capabilities and if possible
re-enabling PSR, this will be added if a panel is found using this
feature.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c703a10d2fd7..cdd9c270b42c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1437,6 +1437,26 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
 	}
 }
 
+static void psr_capability_changed_check(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct i915_psr *psr = &dev_priv->psr;
+	u8 val;
+	int r;
+
+	r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
+	if (r != 1) {
+		DRM_ERROR("Error reading DP_PSR_ESI\n");
+		return;
+	}
+
+	if (val & DP_PSR_CAPS_CHANGE) {
+		intel_psr_disable_locked(intel_dp);
+		psr->sink_not_reliable = true;
+		DRM_DEBUG_KMS("Sink PSR capability changed, disabling PSR\n");
+	}
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1480,6 +1500,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
 
 	psr_alpm_check(intel_dp);
+	psr_capability_changed_check(intel_dp);
 
 exit:
 	mutex_unlock(&psr->lock);
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-11-06  1:45 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-06  1:45 [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation José Roberto de Souza
2019-11-06  1:45 ` [Intel-gfx] " José Roberto de Souza
2019-11-06  1:45 ` [PATCH 2/5] drm/i915/psr: Refactor psr short pulse handler José Roberto de Souza
2019-11-06  1:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-12 17:31   ` Matt Roper
2019-11-12 17:31     ` [Intel-gfx] " Matt Roper
2019-11-06  1:45 ` [PATCH 3/5] drm/i915/psr: Enable ALPM lock timeout error interruption José Roberto de Souza
2019-11-06  1:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-06  1:45 ` José Roberto de Souza [this message]
2019-11-06  1:45   ` [Intel-gfx] [PATCH 4/5] drm/i915/psr: Check if sink PSR capability changed José Roberto de Souza
2019-11-06  1:45 ` [PATCH 5/5] drm/i915/vbt: Parse power conservation features block José Roberto de Souza
2019-11-06  1:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-12 21:21   ` Matt Roper
2019-11-12 21:21     ` [Intel-gfx] " Matt Roper
2019-11-12 23:56     ` Souza, Jose
2019-11-12 23:56       ` [Intel-gfx] " Souza, Jose
2019-11-26  0:47       ` Souza, Jose
2019-11-26  0:47         ` [Intel-gfx] " Souza, Jose
2019-11-27 18:02         ` Matt Roper
2019-11-27 18:02           ` [Intel-gfx] " Matt Roper
2019-11-27 22:48           ` Souza, Jose
2019-11-27 22:48             ` [Intel-gfx] " Souza, Jose
2019-11-06  2:27 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/psr: Add bits per pixel limitation Patchwork
2019-11-06  2:27   ` [Intel-gfx] " Patchwork
2019-11-06 23:24 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-06 23:24   ` [Intel-gfx] " Patchwork
2019-11-12 17:16 ` [PATCH 1/5] " Matt Roper
2019-11-12 17:16   ` [Intel-gfx] " Matt Roper
2019-11-12 18:30   ` Souza, Jose
2019-11-12 18:30     ` [Intel-gfx] " Souza, Jose
2019-11-13 19:15   ` Lucas De Marchi
2019-11-13 19:15     ` [Intel-gfx] " Lucas De Marchi
2019-11-13 19:12 ` Lucas De Marchi
2019-11-13 19:12   ` [Intel-gfx] " Lucas De Marchi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191106014504.167656-4-jose.souza@intel.com \
    --to=jose.souza@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.