From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [PATCH 21/28] drm/i915/gt: Expose engine->mmio_base via sysfs Date: Thu, 7 Nov 2019 08:12:45 +0000 [thread overview] Message-ID: <20191107081252.10542-21-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20191107081252.10542-1-chris@chris-wilson.co.uk> Use the per-engine sysfs directory to let userspace discover the mmio_base of each engine. Prior to recent generations, the user accessible registers on each engine are at a fixed offset relative to each engine -- but require absolute addressing. As the absolute address depends on the actual physical engine, this is not always possible to determine from userspace (for example icl may expose vcs1 or vcs2 as the second vcs engine). Make this easy for userspace to discover by providing the mmio_base in sysfs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c index df263af3a9ea..abddd8d0f9ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c @@ -48,6 +48,15 @@ inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) static struct kobj_attribute inst_attr = __ATTR(instance, 0444, inst_show, NULL); +static ssize_t +mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base); +} + +static struct kobj_attribute mmio_attr = +__ATTR(mmio_base, 0444, mmio_show, NULL); + static const char * const vcs_caps[] = { [ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc", [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc", @@ -170,6 +179,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) &name_attr.attr, &class_attr.attr, &inst_attr.attr, + &mmio_attr.attr, &caps_attr.attr, &all_caps_attr.attr, NULL -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 21/28] drm/i915/gt: Expose engine->mmio_base via sysfs Date: Thu, 7 Nov 2019 08:12:45 +0000 [thread overview] Message-ID: <20191107081252.10542-21-chris@chris-wilson.co.uk> (raw) Message-ID: <20191107081245.T8e2xdnR4EcI4RrChcKtaB9PAQKfc1AxJXSPnAPL2n4@z> (raw) In-Reply-To: <20191107081252.10542-1-chris@chris-wilson.co.uk> Use the per-engine sysfs directory to let userspace discover the mmio_base of each engine. Prior to recent generations, the user accessible registers on each engine are at a fixed offset relative to each engine -- but require absolute addressing. As the absolute address depends on the actual physical engine, this is not always possible to determine from userspace (for example icl may expose vcs1 or vcs2 as the second vcs engine). Make this easy for userspace to discover by providing the mmio_base in sysfs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c index df263af3a9ea..abddd8d0f9ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c @@ -48,6 +48,15 @@ inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) static struct kobj_attribute inst_attr = __ATTR(instance, 0444, inst_show, NULL); +static ssize_t +mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base); +} + +static struct kobj_attribute mmio_attr = +__ATTR(mmio_base, 0444, mmio_show, NULL); + static const char * const vcs_caps[] = { [ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc", [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc", @@ -170,6 +179,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) &name_attr.attr, &class_attr.attr, &inst_attr.attr, + &mmio_attr.attr, &caps_attr.attr, &all_caps_attr.attr, NULL -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-07 8:13 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-07 8:12 [PATCH 01/28] drm/i915: Leave the aliasing-ppgtt size alone Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 02/28] drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY under a separate Kconfig Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 03/28] drm: Expose a method for creating anonymous struct file around drm_minor Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 04/28] drm/i915/selftests: Replace mock_file hackery with drm's true fake Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 05/28] drm/i915/selftests: Wrap vm_mmap() around GEM objects Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 06/28] drm/i915/selftests: Verify mmap_gtt revocation on unbinding Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 07/28] drm/i915/userptr: Try to acquire the page lock around set_page_dirty() Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 08/28] drm/i915/gem: Safely acquire the ctx->vm when copying Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 09/28] drm/i915/selftests: Exercise parallel blit operations on a single ctx Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 10/28] drm/i915/selftests: Perform some basic cycle counting of MI ops Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:39 ` Mika Kuoppala 2019-11-07 8:39 ` [Intel-gfx] " Mika Kuoppala 2019-11-07 8:47 ` Chris Wilson 2019-11-07 8:47 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 11/28] drm/i915/selftests: Mock the engine sorting for easy validation Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 12/28] drm/i915: Use a ctor for TYPESAFE_BY_RCU i915_request Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 13/28] drm/i915: Drop GEM context as a direct link from i915_request Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 14/28] drm/i915: Push the use-semaphore marker onto the intel_context Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 15/28] drm/i915: Remove i915->kernel_context Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 16/28] drm/i915: Move i915_gem_init_contexts() earlier Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 17/28] drm/i915/gt: Defer engine registration until fully initialised Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 12:22 ` Mika Kuoppala 2019-11-07 12:22 ` [Intel-gfx] " Mika Kuoppala 2019-11-07 8:12 ` [PATCH 18/28] drm/i915/gt: Pull GT initialisation under intel_gt_init() Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 19/28] drm/i915/gt: Merge engine init/setup loops Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 20/28] drm/i915/gt: Expose engine properties via sysfs Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` Chris Wilson [this message] 2019-11-07 8:12 ` [Intel-gfx] [PATCH 21/28] drm/i915/gt: Expose engine->mmio_base " Chris Wilson 2019-11-07 8:12 ` [PATCH 22/28] drm/i915/gt: Expose timeslice duration to sysfs Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 23/28] drm/i915/gt: Expose reset stop timeout via sysfs Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 24/28] drm/i915/gt: Expose preempt reset " Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 25/28] drm/i915/gt: Expose heartbeat interval " Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 26/28] drm/i915: Flush idle barriers when waiting Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 27/28] drm/i915: Allow userspace to specify ringsize on construction Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 8:12 ` [PATCH 28/28] drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions Chris Wilson 2019-11-07 8:12 ` [Intel-gfx] " Chris Wilson 2019-11-07 11:18 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/28] drm/i915: Leave the aliasing-ppgtt size alone Patchwork 2019-11-07 11:18 ` [Intel-gfx] " Patchwork 2019-11-07 11:30 ` ✗ Fi.CI.SPARSE: " Patchwork 2019-11-07 11:30 ` [Intel-gfx] " Patchwork 2019-11-07 11:39 ` ✗ Fi.CI.BAT: failure " Patchwork 2019-11-07 11:39 ` [Intel-gfx] " Patchwork
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