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From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: Juergen Gross <jgross@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>,
	Jan Beulich <jbeulich@suse.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: [Xen-devel] [PATCH for-4.13 v4 3/3] x86/vioapic: sync PIR to IRR when modifying entries
Date: Wed, 13 Nov 2019 16:59:40 +0100	[thread overview]
Message-ID: <20191113155940.81837-4-roger.pau@citrix.com> (raw)
In-Reply-To: <20191113155940.81837-1-roger.pau@citrix.com>

If posted interrutps are being used sync PIR to IRR when an unmasked
vIO-APIC entry is modified. Do this in order to prevent vectors in the
IRR being set after a change to a vIO-APIC entry has been performed.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
Cc: Juergen Gross <jgross@suse.com>
---
 xen/arch/x86/hvm/vioapic.c | 46 +++++++++++++++++++++++++++++++++-----
 1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index 9aeef32a14..90e6d1c4e6 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -212,6 +212,44 @@ static int vioapic_hwdom_map_gsi(unsigned int gsi, unsigned int trig,
     return ret;
 }
 
+static inline int pit_channel0_enabled(void)
+{
+    return pt_active(&current->domain->arch.vpit.pt0);
+}
+
+static void sync_vcpus_pir(struct domain *d, union vioapic_redir_entry *ent,
+                           unsigned int irq)
+{
+    DECLARE_BITMAP(vcpus, MAX_VIRT_CPUS) = { };
+
+    switch ( ent->fields.delivery_mode )
+    {
+    case dest_LowestPrio:
+    case dest_Fixed:
+#ifdef IRQ0_SPECIAL_ROUTING
+        if ( (irq == hvm_isa_irq_to_gsi(0)) && pit_channel0_enabled() )
+        {
+            __set_bit(0, vcpus);
+            break;
+        }
+#endif
+        hvm_intr_get_dests(d, ent->fields.dest_id, ent->fields.dest_mode,
+                           ent->fields.delivery_mode, vcpus);
+        break;
+
+    case dest_NMI:
+        /* Nothing to do, NMIs are not signaled on the PIR. */
+        break;
+
+    default:
+        gdprintk(XENLOG_WARNING, "unsupported delivery mode %02u\n",
+                 ent->fields.delivery_mode);
+        break;
+    }
+
+    domain_sync_vlapic_pir(d, vcpus);
+}
+
 static void vioapic_write_redirent(
     struct hvm_vioapic *vioapic, unsigned int idx,
     int top_word, uint32_t val)
@@ -235,6 +273,9 @@ static void vioapic_write_redirent(
     pent = &vioapic->redirtbl[idx];
     ent  = *pent;
 
+    if ( !ent.fields.mask && hvm_funcs.deliver_posted_intr )
+        sync_vcpus_pir(d, pent, vioapic->base_gsi + idx);
+
     if ( top_word )
     {
         /* Contains only the dest_id. */
@@ -391,11 +432,6 @@ static void ioapic_inj_irq(
     vlapic_set_irq(target, vector, trig_mode);
 }
 
-static inline int pit_channel0_enabled(void)
-{
-    return pt_active(&current->domain->arch.vpit.pt0);
-}
-
 static void vioapic_deliver(struct hvm_vioapic *vioapic, unsigned int pin)
 {
     uint16_t dest = vioapic->redirtbl[pin].fields.dest_id;
-- 
2.24.0


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  parent reply	other threads:[~2019-11-13 16:16 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-13 15:59 [Xen-devel] [PATCH for-4.13 v4 0/3] x86/passthrough: fix interrupt migration when using posting Roger Pau Monne
2019-11-13 15:59 ` [Xen-devel] [PATCH for-4.13 v4 1/3] vmx: add ASSERT to prevent syncing PIR to IRR Roger Pau Monne
2019-11-14 12:25   ` Jan Beulich
2019-11-14 13:15     ` Roger Pau Monné
2019-11-13 15:59 ` [Xen-devel] [PATCH for-4.13 v4 2/3] x86/passthrough: fix migration of MSI when using posted interrupts Roger Pau Monne
2019-11-13 21:22   ` Joe Jin
2019-11-14 13:35   ` Jan Beulich
2019-11-14 14:42     ` Roger Pau Monné
2019-11-14 15:35       ` Jan Beulich
2019-11-13 15:59 ` Roger Pau Monne [this message]
2019-11-14 13:49   ` [Xen-devel] [PATCH for-4.13 v4 3/3] x86/vioapic: sync PIR to IRR when modifying entries Jan Beulich

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