From: "Andreas Färber" <afaerber@suse.de>
To: linux-realtek-soc@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, "Andreas Färber" <afaerber@suse.de>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Jason Cooper" <jason@lakedaemon.net>,
"Marc Zyngier" <maz@kernel.org>
Subject: [PATCH v4 4/8] irqchip: rtd1195-mux: Add RTD1195 definitions
Date: Tue, 19 Nov 2019 03:19:13 +0100 [thread overview]
Message-ID: <20191119021917.15917-5-afaerber@suse.de> (raw)
In-Reply-To: <20191119021917.15917-1-afaerber@suse.de>
Add compatible strings and bit mappings for Realtek RTD1195 SoC.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
v3 -> v4:
* Use tabular formatting (Thomas)
* Adopt different braces style (Thomas)
* Updated with shortened isr_to_int_en_mask callback name (Thomas)
* Renamed functions and variables from rtd119x_ to rtd1195_
* Renamed enum values from RTD119X_ to RTD1195_
v3: New
drivers/irqchip/irq-rtd1195-mux.c | 101 +++++++++++++++++++++++++++++++++++++-
1 file changed, 100 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c
index e6b08438b23c..765d72653383 100644
--- a/drivers/irqchip/irq-rtd1195-mux.c
+++ b/drivers/irqchip/irq-rtd1195-mux.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Realtek RTD1295 IRQ mux
+ * Realtek RTD1195/RTD1295 IRQ mux
*
* Copyright (c) 2017-2019 Andreas Färber
*/
@@ -132,6 +132,81 @@ static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = {
.map = rtd1195_mux_irq_domain_map,
};
+enum rtd1195_iso_isr_bits {
+ RTD1195_ISO_ISR_TC3_SHIFT = 1,
+ RTD1195_ISO_ISR_UR0_SHIFT = 2,
+ RTD1195_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1195_ISO_ISR_WDOG_NMI_SHIFT = 7,
+ RTD1195_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1195_ISO_ISR_TC4_SHIFT = 9,
+ RTD1195_ISO_ISR_I2C6_SHIFT = 10,
+ RTD1195_ISO_ISR_RTC_HSEC_SHIFT = 12,
+ RTD1195_ISO_ISR_RTC_ALARM_SHIFT = 13,
+ RTD1195_ISO_ISR_VFD_WDONE_SHIFT = 14,
+ RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT = 15,
+ RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT = 16,
+ RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT = 17,
+ RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT = 18,
+ RTD1195_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1195_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1195_ISO_ISR_CEC_SHIFT = 22,
+};
+
+static const u32 rtd1195_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1195_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1195_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1195_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1195_ISO_ISR_I2C6_SHIFT] = BIT(10),
+ [RTD1195_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12),
+ [RTD1195_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13),
+ [RTD1195_ISO_ISR_VFD_WDONE_SHIFT] = BIT(14),
+ [RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT] = BIT(15),
+ [RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT] = BIT(16),
+ [RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT] = BIT(17),
+ [RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT] = BIT(18),
+ [RTD1195_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1195_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1195_ISO_ISR_CEC_SHIFT] = BIT(22),
+};
+
+enum rtd1195_misc_isr_bits {
+ RTD1195_MIS_ISR_WDOG_NMI_SHIFT = 2,
+ RTD1195_MIS_ISR_UR1_SHIFT = 3,
+ RTD1195_MIS_ISR_I2C1_SHIFT = 4,
+ RTD1195_MIS_ISR_UR1_TO_SHIFT = 5,
+ RTD1195_MIS_ISR_TC0_SHIFT = 6,
+ RTD1195_MIS_ISR_TC1_SHIFT = 7,
+ RTD1195_MIS_ISR_RTC_HSEC_SHIFT = 9,
+ RTD1195_MIS_ISR_RTC_MIN_SHIFT = 10,
+ RTD1195_MIS_ISR_RTC_HOUR_SHIFT = 11,
+ RTD1195_MIS_ISR_RTC_DATE_SHIFT = 12,
+ RTD1195_MIS_ISR_I2C5_SHIFT = 14,
+ RTD1195_MIS_ISR_I2C4_SHIFT = 15,
+ RTD1195_MIS_ISR_GPIOA_SHIFT = 19,
+ RTD1195_MIS_ISR_GPIODA_SHIFT = 20,
+ RTD1195_MIS_ISR_LSADC_SHIFT = 21,
+ RTD1195_MIS_ISR_I2C3_SHIFT = 23,
+ RTD1195_MIS_ISR_I2C2_SHIFT = 26,
+ RTD1195_MIS_ISR_GSPI_SHIFT = 27,
+};
+
+static const u32 rtd1195_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1195_MIS_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1195_MIS_ISR_I2C1_SHIFT] = BIT(4),
+ [RTD1195_MIS_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1195_MIS_ISR_RTC_MIN_SHIFT] = BIT(10),
+ [RTD1195_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11),
+ [RTD1195_MIS_ISR_RTC_DATE_SHIFT] = BIT(12),
+ [RTD1195_MIS_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1195_MIS_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1195_MIS_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1195_MIS_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1195_MIS_ISR_LSADC_SHIFT] = BIT(21),
+ [RTD1195_MIS_ISR_I2C2_SHIFT] = BIT(26),
+ [RTD1195_MIS_ISR_GSPI_SHIFT] = BIT(27),
+ [RTD1195_MIS_ISR_I2C3_SHIFT] = BIT(28),
+};
+
enum rtd1295_iso_isr_bits {
RTD1295_ISO_ISR_UR0_SHIFT = 2,
RTD1295_ISO_ISR_IRDA_SHIFT = 5,
@@ -202,6 +277,13 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = {
[RTD1295_ISR_FAN_SHIFT] = BIT(29),
};
+static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = {
+ .isr_offset = 0x0,
+ .umsk_isr_offset = 0x4,
+ .scpu_int_en_offset = 0x40,
+ .isr_to_int_en_mask = rtd1195_iso_isr_to_scpu_int_en_mask,
+};
+
static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
.isr_offset = 0x0,
.umsk_isr_offset = 0x4,
@@ -209,6 +291,13 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
.isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask,
};
+static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = {
+ .umsk_isr_offset = 0x8,
+ .isr_offset = 0xc,
+ .scpu_int_en_offset = 0x80,
+ .isr_to_int_en_mask = rtd1195_misc_isr_to_scpu_int_en_mask,
+};
+
static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
.umsk_isr_offset = 0x8,
.isr_offset = 0xc,
@@ -217,10 +306,18 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
};
static const struct of_device_id rtd1295_irq_mux_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1195-iso-irq-mux",
+ .data = &rtd1195_iso_irq_mux_info,
+ },
{
.compatible = "realtek,rtd1295-iso-irq-mux",
.data = &rtd1295_iso_irq_mux_info,
},
+ {
+ .compatible = "realtek,rtd1195-misc-irq-mux",
+ .data = &rtd1195_misc_irq_mux_info,
+ },
{
.compatible = "realtek,rtd1295-misc-irq-mux",
.data = &rtd1295_misc_irq_mux_info,
@@ -279,5 +376,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node,
return 0;
}
+IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init);
IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init);
+IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init);
IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init);
--
2.16.4
WARNING: multiple messages have this Message-ID (diff)
From: "Andreas Färber" <afaerber@suse.de>
To: linux-realtek-soc@lists.infradead.org
Cc: "Jason Cooper" <jason@lakedaemon.net>,
"Marc Zyngier" <maz@kernel.org>,
linux-kernel@vger.kernel.org,
"Thomas Gleixner" <tglx@linutronix.de>,
"Andreas Färber" <afaerber@suse.de>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 4/8] irqchip: rtd1195-mux: Add RTD1195 definitions
Date: Tue, 19 Nov 2019 03:19:13 +0100 [thread overview]
Message-ID: <20191119021917.15917-5-afaerber@suse.de> (raw)
In-Reply-To: <20191119021917.15917-1-afaerber@suse.de>
Add compatible strings and bit mappings for Realtek RTD1195 SoC.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
v3 -> v4:
* Use tabular formatting (Thomas)
* Adopt different braces style (Thomas)
* Updated with shortened isr_to_int_en_mask callback name (Thomas)
* Renamed functions and variables from rtd119x_ to rtd1195_
* Renamed enum values from RTD119X_ to RTD1195_
v3: New
drivers/irqchip/irq-rtd1195-mux.c | 101 +++++++++++++++++++++++++++++++++++++-
1 file changed, 100 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c
index e6b08438b23c..765d72653383 100644
--- a/drivers/irqchip/irq-rtd1195-mux.c
+++ b/drivers/irqchip/irq-rtd1195-mux.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Realtek RTD1295 IRQ mux
+ * Realtek RTD1195/RTD1295 IRQ mux
*
* Copyright (c) 2017-2019 Andreas Färber
*/
@@ -132,6 +132,81 @@ static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = {
.map = rtd1195_mux_irq_domain_map,
};
+enum rtd1195_iso_isr_bits {
+ RTD1195_ISO_ISR_TC3_SHIFT = 1,
+ RTD1195_ISO_ISR_UR0_SHIFT = 2,
+ RTD1195_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1195_ISO_ISR_WDOG_NMI_SHIFT = 7,
+ RTD1195_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1195_ISO_ISR_TC4_SHIFT = 9,
+ RTD1195_ISO_ISR_I2C6_SHIFT = 10,
+ RTD1195_ISO_ISR_RTC_HSEC_SHIFT = 12,
+ RTD1195_ISO_ISR_RTC_ALARM_SHIFT = 13,
+ RTD1195_ISO_ISR_VFD_WDONE_SHIFT = 14,
+ RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT = 15,
+ RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT = 16,
+ RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT = 17,
+ RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT = 18,
+ RTD1195_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1195_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1195_ISO_ISR_CEC_SHIFT = 22,
+};
+
+static const u32 rtd1195_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1195_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1195_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1195_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1195_ISO_ISR_I2C6_SHIFT] = BIT(10),
+ [RTD1195_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12),
+ [RTD1195_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13),
+ [RTD1195_ISO_ISR_VFD_WDONE_SHIFT] = BIT(14),
+ [RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT] = BIT(15),
+ [RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT] = BIT(16),
+ [RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT] = BIT(17),
+ [RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT] = BIT(18),
+ [RTD1195_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1195_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1195_ISO_ISR_CEC_SHIFT] = BIT(22),
+};
+
+enum rtd1195_misc_isr_bits {
+ RTD1195_MIS_ISR_WDOG_NMI_SHIFT = 2,
+ RTD1195_MIS_ISR_UR1_SHIFT = 3,
+ RTD1195_MIS_ISR_I2C1_SHIFT = 4,
+ RTD1195_MIS_ISR_UR1_TO_SHIFT = 5,
+ RTD1195_MIS_ISR_TC0_SHIFT = 6,
+ RTD1195_MIS_ISR_TC1_SHIFT = 7,
+ RTD1195_MIS_ISR_RTC_HSEC_SHIFT = 9,
+ RTD1195_MIS_ISR_RTC_MIN_SHIFT = 10,
+ RTD1195_MIS_ISR_RTC_HOUR_SHIFT = 11,
+ RTD1195_MIS_ISR_RTC_DATE_SHIFT = 12,
+ RTD1195_MIS_ISR_I2C5_SHIFT = 14,
+ RTD1195_MIS_ISR_I2C4_SHIFT = 15,
+ RTD1195_MIS_ISR_GPIOA_SHIFT = 19,
+ RTD1195_MIS_ISR_GPIODA_SHIFT = 20,
+ RTD1195_MIS_ISR_LSADC_SHIFT = 21,
+ RTD1195_MIS_ISR_I2C3_SHIFT = 23,
+ RTD1195_MIS_ISR_I2C2_SHIFT = 26,
+ RTD1195_MIS_ISR_GSPI_SHIFT = 27,
+};
+
+static const u32 rtd1195_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1195_MIS_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1195_MIS_ISR_I2C1_SHIFT] = BIT(4),
+ [RTD1195_MIS_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1195_MIS_ISR_RTC_MIN_SHIFT] = BIT(10),
+ [RTD1195_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11),
+ [RTD1195_MIS_ISR_RTC_DATE_SHIFT] = BIT(12),
+ [RTD1195_MIS_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1195_MIS_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1195_MIS_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1195_MIS_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1195_MIS_ISR_LSADC_SHIFT] = BIT(21),
+ [RTD1195_MIS_ISR_I2C2_SHIFT] = BIT(26),
+ [RTD1195_MIS_ISR_GSPI_SHIFT] = BIT(27),
+ [RTD1195_MIS_ISR_I2C3_SHIFT] = BIT(28),
+};
+
enum rtd1295_iso_isr_bits {
RTD1295_ISO_ISR_UR0_SHIFT = 2,
RTD1295_ISO_ISR_IRDA_SHIFT = 5,
@@ -202,6 +277,13 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = {
[RTD1295_ISR_FAN_SHIFT] = BIT(29),
};
+static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = {
+ .isr_offset = 0x0,
+ .umsk_isr_offset = 0x4,
+ .scpu_int_en_offset = 0x40,
+ .isr_to_int_en_mask = rtd1195_iso_isr_to_scpu_int_en_mask,
+};
+
static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
.isr_offset = 0x0,
.umsk_isr_offset = 0x4,
@@ -209,6 +291,13 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
.isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask,
};
+static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = {
+ .umsk_isr_offset = 0x8,
+ .isr_offset = 0xc,
+ .scpu_int_en_offset = 0x80,
+ .isr_to_int_en_mask = rtd1195_misc_isr_to_scpu_int_en_mask,
+};
+
static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
.umsk_isr_offset = 0x8,
.isr_offset = 0xc,
@@ -217,10 +306,18 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
};
static const struct of_device_id rtd1295_irq_mux_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1195-iso-irq-mux",
+ .data = &rtd1195_iso_irq_mux_info,
+ },
{
.compatible = "realtek,rtd1295-iso-irq-mux",
.data = &rtd1295_iso_irq_mux_info,
},
+ {
+ .compatible = "realtek,rtd1195-misc-irq-mux",
+ .data = &rtd1195_misc_irq_mux_info,
+ },
{
.compatible = "realtek,rtd1295-misc-irq-mux",
.data = &rtd1295_misc_irq_mux_info,
@@ -279,5 +376,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node,
return 0;
}
+IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init);
IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init);
+IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init);
IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init);
--
2.16.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-19 2:19 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-19 2:19 [PATCH v4 0/8] ARM: Realtek RTD1195/RTD1295/RTD1395 IRQ mux Andreas Färber
2019-11-19 2:19 ` Andreas Färber
2019-11-19 2:19 ` [PATCH v4 1/8] dt-bindings: interrupt-controller: Add Realtek RTD1195/RTD1295 mux Andreas Färber
2019-11-19 2:19 ` Andreas Färber
2019-11-19 2:19 ` [PATCH v4 2/8] irqchip: Add Realtek RTD1295 mux driver Andreas Färber
2019-11-19 2:19 ` Andreas Färber
2019-11-19 12:01 ` Marc Zyngier
2019-11-19 12:01 ` Marc Zyngier
2019-11-19 20:56 ` Andreas Färber
2019-11-19 20:56 ` Andreas Färber
2019-11-19 22:29 ` Marc Zyngier
2019-11-19 22:29 ` Marc Zyngier
2019-11-19 23:33 ` Andreas Färber
2019-11-19 23:33 ` Andreas Färber
2019-11-20 10:20 ` Marc Zyngier
2019-11-20 10:20 ` Marc Zyngier
2019-11-20 13:34 ` Andreas Färber
2019-11-20 13:34 ` Andreas Färber
2019-11-20 14:32 ` Marc Zyngier
2019-11-20 14:32 ` Marc Zyngier
2019-11-19 23:25 ` Andreas Färber
2019-11-19 23:25 ` Andreas Färber
2019-11-20 10:18 ` Marc Zyngier
2019-11-20 10:18 ` Marc Zyngier
2019-11-20 12:12 ` Andreas Färber
2019-11-20 12:12 ` Andreas Färber
2019-11-20 12:23 ` Marc Zyngier
2019-11-20 12:23 ` Marc Zyngier
2019-11-19 2:19 ` [PATCH v4 3/8] arm64: dts: realtek: rtd129x: Add irq muxes and UART interrupts Andreas Färber
2019-11-19 2:19 ` Andreas Färber
2019-11-19 2:19 ` Andreas Färber [this message]
2019-11-19 2:19 ` [PATCH v4 4/8] irqchip: rtd1195-mux: Add RTD1195 definitions Andreas Färber
2019-11-19 2:19 ` [PATCH v4 5/8] ARM: dts: rtd1195: Add irq muxes and UART interrupts Andreas Färber
2019-11-19 2:19 ` Andreas Färber
2019-11-19 2:19 ` [PATCH v4 6/8] dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395 Andreas Färber
2019-11-19 2:19 ` Andreas Färber
2019-11-19 2:19 ` [PATCH v4 7/8] irqchip: rtd1195-mux: Add RTD1395 definitions Andreas Färber
2019-11-19 2:19 ` Andreas Färber
2019-11-19 2:19 ` [PATCH v4 8/8] arm64: dts: realtek: rtd139x: Add irq muxes and UART interrupts Andreas Färber
2019-11-19 2:19 ` Andreas Färber
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191119021917.15917-5-afaerber@suse.de \
--to=afaerber@suse.de \
--cc=jason@lakedaemon.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-realtek-soc@lists.infradead.org \
--cc=maz@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.