From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 0/7] target-arm queue
Date: Tue, 19 Nov 2019 13:31:38 +0000 [thread overview]
Message-ID: <20191119133145.31466-1-peter.maydell@linaro.org> (raw)
Target-arm queue for rc2 -- just some minor bugfixes.
thanks
-- PMM
The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417:
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119
for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062:
target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000)
----------------------------------------------------------------
target-arm queue:
* Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
* Relax r13 restriction for ldrex/strex for v8.0
* Do not reject rt == rt2 for strexd
* net/cadence_gem: Set PHY autonegotiation restart status
* ssi: xilinx_spips: Skip spi bus update for a few register writes
* pl031: Expose RTCICR as proper WC register
----------------------------------------------------------------
Alexander Graf (1):
pl031: Expose RTCICR as proper WC register
Linus Ziegert (1):
net/cadence_gem: Set PHY autonegotiation restart status
Richard Henderson (4):
target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
target/arm: Do not reject rt == rt2 for strexd
target/arm: Relax r13 restriction for ldrex/strex for v8.0
target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
Sai Pavan Boddu (1):
ssi: xilinx_spips: Skip spi bus update for a few register writes
target/arm/cpu.h | 5 +--
hw/net/cadence_gem.c | 9 ++--
hw/rtc/pl031.c | 6 +--
hw/ssi/xilinx_spips.c | 22 ++++++++--
target/arm/cpu64.c | 15 -------
target/arm/helper.c | 9 +++-
target/arm/m_helper.c | 114 ++++++++++++++++++++++++++++++-------------------
target/arm/translate.c | 14 +++---
8 files changed, 113 insertions(+), 81 deletions(-)
next reply other threads:[~2019-11-19 13:34 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-19 13:31 Peter Maydell [this message]
2019-11-19 13:31 ` [PULL 1/7] pl031: Expose RTCICR as proper WC register Peter Maydell
2019-11-19 13:31 ` [PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller Peter Maydell
2019-11-19 13:31 ` [PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes Peter Maydell
2019-11-19 13:31 ` [PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status Peter Maydell
2019-11-19 13:31 ` [PULL 5/7] target/arm: Do not reject rt == rt2 for strexd Peter Maydell
2019-11-19 13:31 ` [PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0 Peter Maydell
2019-11-19 13:31 ` [PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY Peter Maydell
2019-11-19 15:55 ` [PULL 0/7] target-arm queue Peter Maydell
2020-07-27 15:19 Peter Maydell
2020-07-28 18:43 ` Peter Maydell
2021-03-23 14:26 Peter Maydell
2021-03-23 22:28 ` Peter Maydell
2022-11-04 11:35 Peter Maydell
2022-11-05 12:34 ` Stefan Hajnoczi
2023-07-17 12:47 Peter Maydell
2023-07-17 19:12 ` Richard Henderson
2024-03-25 12:35 Peter Maydell
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