From: Ramalingam C <ramalingam.c@intel.com> To: intel-gfx <intel-gfx@lists.freedesktop.org> Subject: [PATCH 2/2] drm/i915: Skip the Wa_1604555607 verification Date: Wed, 20 Nov 2019 23:01:55 +0530 [thread overview] Message-ID: <20191120173155.20168-3-ramalingam.c@intel.com> (raw) In-Reply-To: <20191120173155.20168-1-ramalingam.c@intel.com> At TGL A0 stepping, FF_MODE2 register read back is broken, hence disabling the WA verification. Helper function called wa_write_masked_or_no_verify is defined for the same purpose. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 93efefa205d6..1698330c6f23 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -160,6 +160,20 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, _wa_add(wal, &wa); } +static void +wa_write_masked_or_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, + u32 val) +{ + struct i915_wa wa = { + .reg = reg, + .mask = mask, + .val = val, + .read = 0, + }; + + _wa_add(wal, &wa); +} + static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { @@ -578,7 +592,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, val = intel_uncore_read(engine->uncore, FF_MODE2); val &= ~FF_MODE2_TDS_TIMER_MASK; val |= FF_MODE2_TDS_TIMER_128; - wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val); + if (IS_TGL_REVID(engine->uncore->i915, 0, TGL_REVID_A0)) + wa_write_masked_or_no_verify(wal, FF_MODE2, + FF_MODE2_TDS_TIMER_MASK, val); + else + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val); } static void -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com> To: intel-gfx <intel-gfx@lists.freedesktop.org> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Skip the Wa_1604555607 verification Date: Wed, 20 Nov 2019 23:01:55 +0530 [thread overview] Message-ID: <20191120173155.20168-3-ramalingam.c@intel.com> (raw) Message-ID: <20191120173155.-PDW91WIDBU9jvroTo6ND62dySXU1-AnhMp8_NrlWKU@z> (raw) In-Reply-To: <20191120173155.20168-1-ramalingam.c@intel.com> At TGL A0 stepping, FF_MODE2 register read back is broken, hence disabling the WA verification. Helper function called wa_write_masked_or_no_verify is defined for the same purpose. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 93efefa205d6..1698330c6f23 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -160,6 +160,20 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, _wa_add(wal, &wa); } +static void +wa_write_masked_or_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, + u32 val) +{ + struct i915_wa wa = { + .reg = reg, + .mask = mask, + .val = val, + .read = 0, + }; + + _wa_add(wal, &wa); +} + static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { @@ -578,7 +592,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, val = intel_uncore_read(engine->uncore, FF_MODE2); val &= ~FF_MODE2_TDS_TIMER_MASK; val |= FF_MODE2_TDS_TIMER_128; - wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val); + if (IS_TGL_REVID(engine->uncore->i915, 0, TGL_REVID_A0)) + wa_write_masked_or_no_verify(wal, FF_MODE2, + FF_MODE2_TDS_TIMER_MASK, val); + else + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val); } static void -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-20 17:32 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-20 17:31 [PATCH 0/2] Wa_1604555607 implementation and verification skip Ramalingam C 2019-11-20 17:31 ` [Intel-gfx] " Ramalingam C 2019-11-20 17:31 ` [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C 2019-11-20 17:31 ` [Intel-gfx] " Ramalingam C 2019-11-20 17:31 ` Ramalingam C [this message] 2019-11-20 17:31 ` [Intel-gfx] [PATCH 2/2] drm/i915: Skip the Wa_1604555607 verification Ramalingam C 2019-11-20 17:50 ` Tvrtko Ursulin 2019-11-20 17:50 ` [Intel-gfx] " Tvrtko Ursulin 2019-11-20 17:58 ` Lucas De Marchi 2019-11-20 17:58 ` [Intel-gfx] " Lucas De Marchi 2019-11-20 18:05 ` Ramalingam C 2019-11-20 18:05 ` [Intel-gfx] " Ramalingam C 2019-11-21 5:44 ` Ramalingam C 2019-11-21 5:44 ` [Intel-gfx] " Ramalingam C 2019-11-20 23:21 ` ✗ Fi.CI.CHECKPATCH: warning for Wa_1604555607 implementation and verification skip (rev2) Patchwork 2019-11-20 23:21 ` [Intel-gfx] " Patchwork 2019-11-20 23:44 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-20 23:44 ` [Intel-gfx] " Patchwork 2019-11-21 5:58 ` ✗ Fi.CI.CHECKPATCH: warning for Wa_1604555607 implementation and verification skip (rev3) Patchwork 2019-11-21 5:58 ` [Intel-gfx] " Patchwork 2019-11-21 6:35 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-21 6:35 ` [Intel-gfx] " Patchwork
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