From: Bjorn Helgaas <helgaas@kernel.org>
To: linux-pci@vger.kernel.org
Cc: Alex Deucher <alexdeucher@gmail.com>,
Frederick Lawler <fred@fredlawl.com>,
Christian Koenig <christian.koenig@amd.com>,
Chunming Zhou <David1.Zhou@amd.com>,
Dave Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
amd-gfx@lists.freedesktop.org,
Bjorn Helgaas <bhelgaas@google.com>,
Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 2/7] drm/amdgpu: Correct Transmit Margin masks
Date: Thu, 21 Nov 2019 08:02:15 -0600 [thread overview]
Message-ID: <20191121140220.38030-3-helgaas@kernel.org> (raw)
In-Reply-To: <20191121140220.38030-1-helgaas@kernel.org>
From: Bjorn Helgaas <bhelgaas@google.com>
Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.
Correct the mask to "7 << 7", which is the Transmit Margin field.
Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb3..13a5696d2a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 493af42152f2..1e350172dc7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
--
2.24.0.432.g9d3f5f5b63-goog
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: linux-pci@vger.kernel.org
Cc: Frederick Lawler <fred@fredlawl.com>,
Dave Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Bjorn Helgaas <bhelgaas@google.com>,
amd-gfx@lists.freedesktop.org,
Alex Deucher <alexander.deucher@amd.com>,
Christian Koenig <christian.koenig@amd.com>
Subject: [PATCH 2/7] drm/amdgpu: Correct Transmit Margin masks
Date: Thu, 21 Nov 2019 08:02:15 -0600 [thread overview]
Message-ID: <20191121140220.38030-3-helgaas@kernel.org> (raw)
Message-ID: <20191121140215.pwsRmlmRtz4PDe48PR3fVpxrEH9urRYMsR1s9y2uXeE@z> (raw)
In-Reply-To: <20191121140220.38030-1-helgaas@kernel.org>
From: Bjorn Helgaas <bhelgaas@google.com>
Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.
Correct the mask to "7 << 7", which is the Transmit Margin field.
Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb3..13a5696d2a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 493af42152f2..1e350172dc7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
--
2.24.0.432.g9d3f5f5b63-goog
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: linux-pci@vger.kernel.org
Cc: Chunming Zhou <David1.Zhou@amd.com>,
Frederick Lawler <fred@fredlawl.com>,
Dave Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Bjorn Helgaas <bhelgaas@google.com>,
amd-gfx@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>,
Alex Deucher <alexdeucher@gmail.com>,
Alex Deucher <alexander.deucher@amd.com>,
Christian Koenig <christian.koenig@amd.com>
Subject: [PATCH 2/7] drm/amdgpu: Correct Transmit Margin masks
Date: Thu, 21 Nov 2019 08:02:15 -0600 [thread overview]
Message-ID: <20191121140220.38030-3-helgaas@kernel.org> (raw)
Message-ID: <20191121140215.GuVpFmxk9jAwLcA_EotzkyRbj97LAcOseCfLO15JBd0@z> (raw)
In-Reply-To: <20191121140220.38030-1-helgaas@kernel.org>
From: Bjorn Helgaas <bhelgaas@google.com>
Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.
Correct the mask to "7 << 7", which is the Transmit Margin field.
Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb3..13a5696d2a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 493af42152f2..1e350172dc7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
--
2.24.0.432.g9d3f5f5b63-goog
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2019-11-21 14:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-21 14:02 [PATCH v2 0/7] PCI: Prefer pcie_capability_read_word() Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` [PATCH 1/7] PCI: Add #defines for Enter Compliance, Transmit Margin Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas [this message]
2019-11-21 14:02 ` [PATCH 2/7] drm/amdgpu: Correct Transmit Margin masks Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` [PATCH 3/7] drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` [PATCH 4/7] drm/amdgpu: Prefer pcie_capability_read_word() Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` [PATCH 5/7] drm/radeon: Correct Transmit Margin masks Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` [PATCH 6/7] drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` [PATCH 7/7] drm/radeon: Prefer pcie_capability_read_word() Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 14:02 ` Bjorn Helgaas
2019-11-21 16:37 ` [PATCH v2 0/7] PCI: " Deucher, Alexander
2019-11-21 16:37 ` Deucher, Alexander
2019-11-21 16:37 ` Deucher, Alexander
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