From: Brian Masney <masneyb@onstation.org> To: robdclark@gmail.com, sean@poorly.run, robh+dt@kernel.org Cc: airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: drm/msm/gpu: document second interconnect Date: Thu, 21 Nov 2019 20:26:42 -0500 [thread overview] Message-ID: <20191122012645.7430-2-masneyb@onstation.org> (raw) In-Reply-To: <20191122012645.7430-1-masneyb@onstation.org> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. There's a separate interconnect path that needs to be setup to OCMEM. Let's document this second interconnect path that's available. Since there's now two available interconnects, let's add the interconnect-names property. Signed-off-by: Brian Masney <masneyb@onstation.org> --- Documentation/devicetree/bindings/display/msm/gpu.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 2b8fd26c43b0..3e6cd3f64a78 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -23,7 +23,10 @@ Required properties: - iommus: optional phandle to an adreno iommu instance - operating-points-v2: optional phandle to the OPP operating points - interconnects: optional phandle to an interconnect provider. See - ../interconnect/interconnect.txt for details. + ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms + will have two paths; all others will have one path. +- interconnect-names: The names of the interconnect paths that correspond to the + interconnects property. Values must be gfx-mem and ocmem. - qcom,gmu: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. Applicable targets: - qcom,adreno-630.2 @@ -76,6 +79,7 @@ Example a6xx (with GMU): operating-points-v2 = <&gpu_opp_table>; interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + interconnect-names = "gfx-mem"; qcom,gmu = <&gmu>; -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Brian Masney <masneyb@onstation.org> To: robdclark@gmail.com, sean@poorly.run, robh+dt@kernel.org Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, airlied@linux.ie, linux-arm-msm@vger.kernel.org, dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 1/4] dt-bindings: drm/msm/gpu: document second interconnect Date: Thu, 21 Nov 2019 20:26:42 -0500 [thread overview] Message-ID: <20191122012645.7430-2-masneyb@onstation.org> (raw) Message-ID: <20191122012642.fmCeMl6bJl3vjBlkSrPcYlUeDA_7NI466mUUxpN37BM@z> (raw) In-Reply-To: <20191122012645.7430-1-masneyb@onstation.org> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. There's a separate interconnect path that needs to be setup to OCMEM. Let's document this second interconnect path that's available. Since there's now two available interconnects, let's add the interconnect-names property. Signed-off-by: Brian Masney <masneyb@onstation.org> --- Documentation/devicetree/bindings/display/msm/gpu.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 2b8fd26c43b0..3e6cd3f64a78 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -23,7 +23,10 @@ Required properties: - iommus: optional phandle to an adreno iommu instance - operating-points-v2: optional phandle to the OPP operating points - interconnects: optional phandle to an interconnect provider. See - ../interconnect/interconnect.txt for details. + ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms + will have two paths; all others will have one path. +- interconnect-names: The names of the interconnect paths that correspond to the + interconnects property. Values must be gfx-mem and ocmem. - qcom,gmu: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. Applicable targets: - qcom,adreno-630.2 @@ -76,6 +79,7 @@ Example a6xx (with GMU): operating-points-v2 = <&gpu_opp_table>; interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + interconnect-names = "gfx-mem"; qcom,gmu = <&gmu>; -- 2.21.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2019-11-22 1:27 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-22 1:26 [PATCH v2 0/4] drm/msm/gpu: add support for ocmem interconnect Brian Masney 2019-11-22 1:26 ` Brian Masney 2019-11-22 1:26 ` Brian Masney [this message] 2019-11-22 1:26 ` [PATCH v2 1/4] dt-bindings: drm/msm/gpu: document second interconnect Brian Masney 2019-12-04 19:36 ` Rob Herring 2019-12-04 19:36 ` Rob Herring 2019-12-12 7:14 ` Bjorn Andersson 2019-12-12 7:14 ` Bjorn Andersson 2019-11-22 1:26 ` [PATCH v2 2/4] drm/msm/gpu: add support for ocmem interconnect path Brian Masney 2019-11-22 1:26 ` Brian Masney 2019-11-22 1:26 ` Brian Masney 2019-12-12 7:12 ` Bjorn Andersson 2019-12-12 7:12 ` Bjorn Andersson 2019-11-22 1:26 ` [PATCH v2 3/4] drm/msm/a3xx: set interconnect bandwidth vote Brian Masney 2019-11-22 1:26 ` Brian Masney 2019-11-22 1:26 ` Brian Masney 2019-12-12 7:17 ` Bjorn Andersson 2019-12-12 7:17 ` Bjorn Andersson 2019-11-22 1:26 ` [PATCH v2 4/4] drm/msm/a4xx: " Brian Masney 2019-11-22 1:26 ` Brian Masney 2019-12-12 7:18 ` Bjorn Andersson 2019-12-12 7:18 ` Bjorn Andersson
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