From: "Andreas Färber" <afaerber@suse.de> To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, "Andreas Färber" <afaerber@suse.de>, "Russell King" <linux@armlinux.org.uk> Subject: [PATCH v4 8/8] ARM: realtek: Enable RTD1195 arch timer Date: Sat, 23 Nov 2019 21:37:59 +0100 [thread overview] Message-ID: <20191123203759.20708-9-afaerber@suse.de> (raw) In-Reply-To: <20191123203759.20708-1-afaerber@suse.de> Without this magic write the timer doesn't work and boot gets stuck. Signed-off-by: Andreas Färber <afaerber@suse.de> --- What is the name of the register 0xff018000? Is 0x1 a BIT(0) write, or how are the register bits defined? Is this a reset or a clock gate? How should we model it in DT? v3 -> v4: * Use writel_relaxed() instead of writel() v2 -> v3: Unchanged v2: New arch/arm/mach-realtek/rtd1195.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-realtek/rtd1195.c b/arch/arm/mach-realtek/rtd1195.c index 0381a4447384..8d4de0c2308d 100644 --- a/arch/arm/mach-realtek/rtd1195.c +++ b/arch/arm/mach-realtek/rtd1195.c @@ -5,6 +5,9 @@ * Copyright (c) 2017-2019 Andreas Färber */ +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/io.h> #include <linux/memblock.h> #include <asm/mach/arch.h> @@ -27,6 +30,18 @@ static void __init rtd1195_reserve(void) rtd1195_memblock_remove(0x18100000, 0x01000000); } +static void __init rtd1195_init_time(void) +{ + void __iomem *base; + + base = ioremap(0xff018000, 4); + writel_relaxed(0x1, base); + iounmap(base); + + of_clk_init(NULL); + timer_probe(); +} + static const char *const rtd1195_dt_compat[] __initconst = { "realtek,rtd1195", NULL @@ -34,6 +49,7 @@ static const char *const rtd1195_dt_compat[] __initconst = { DT_MACHINE_START(rtd1195, "Realtek RTD1195") .dt_compat = rtd1195_dt_compat, + .init_time = rtd1195_init_time, .reserve = rtd1195_reserve, .l2c_aux_val = 0x0, .l2c_aux_mask = ~0x0, -- 2.16.4
WARNING: multiple messages have this Message-ID (diff)
From: "Andreas Färber" <afaerber@suse.de> To: linux-realtek-soc@lists.infradead.org Cc: "Russell King" <linux@armlinux.org.uk>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Andreas Färber" <afaerber@suse.de> Subject: [PATCH v4 8/8] ARM: realtek: Enable RTD1195 arch timer Date: Sat, 23 Nov 2019 21:37:59 +0100 [thread overview] Message-ID: <20191123203759.20708-9-afaerber@suse.de> (raw) In-Reply-To: <20191123203759.20708-1-afaerber@suse.de> Without this magic write the timer doesn't work and boot gets stuck. Signed-off-by: Andreas Färber <afaerber@suse.de> --- What is the name of the register 0xff018000? Is 0x1 a BIT(0) write, or how are the register bits defined? Is this a reset or a clock gate? How should we model it in DT? v3 -> v4: * Use writel_relaxed() instead of writel() v2 -> v3: Unchanged v2: New arch/arm/mach-realtek/rtd1195.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-realtek/rtd1195.c b/arch/arm/mach-realtek/rtd1195.c index 0381a4447384..8d4de0c2308d 100644 --- a/arch/arm/mach-realtek/rtd1195.c +++ b/arch/arm/mach-realtek/rtd1195.c @@ -5,6 +5,9 @@ * Copyright (c) 2017-2019 Andreas Färber */ +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/io.h> #include <linux/memblock.h> #include <asm/mach/arch.h> @@ -27,6 +30,18 @@ static void __init rtd1195_reserve(void) rtd1195_memblock_remove(0x18100000, 0x01000000); } +static void __init rtd1195_init_time(void) +{ + void __iomem *base; + + base = ioremap(0xff018000, 4); + writel_relaxed(0x1, base); + iounmap(base); + + of_clk_init(NULL); + timer_probe(); +} + static const char *const rtd1195_dt_compat[] __initconst = { "realtek,rtd1195", NULL @@ -34,6 +49,7 @@ static const char *const rtd1195_dt_compat[] __initconst = { DT_MACHINE_START(rtd1195, "Realtek RTD1195") .dt_compat = rtd1195_dt_compat, + .init_time = rtd1195_init_time, .reserve = rtd1195_reserve, .l2c_aux_val = 0x0, .l2c_aux_mask = ~0x0, -- 2.16.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-23 20:38 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-23 20:37 [PATCH v4 0/8] ARM: Initial RTD1195 and MeLE X1000 & Horseradish support Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2019-11-23 20:37 ` [PATCH v4 1/8] dt-bindings: arm: realtek: Add RTD1195 and MeLE X1000 Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2019-11-23 20:37 ` [PATCH v4 2/8] ARM: Prepare Realtek RTD1195 Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2020-01-05 5:52 ` Andreas Färber 2020-01-05 5:52 ` Andreas Färber 2020-01-15 13:22 ` Andreas Färber 2020-01-15 13:22 ` Andreas Färber 2019-11-23 20:37 ` [PATCH v4 3/8] ARM: dts: Prepare Realtek RTD1195 and MeLE X1000 Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2019-11-23 20:37 ` [PATCH v4 4/8] ARM: dts: rtd1195: Exclude boot ROM from memory ranges Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2019-11-23 20:37 ` [PATCH v4 5/8] ARM: dts: rtd1195: Introduce r-bus Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2019-11-23 20:37 ` [PATCH v4 6/8] dt-bindings: arm: realtek: Add Realtek Horseradish EVB Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2019-12-05 15:18 ` Rob Herring 2019-12-05 15:18 ` Rob Herring 2019-11-23 20:37 ` [PATCH v4 7/8] ARM: dts: rtd1195: " Andreas Färber 2019-11-23 20:37 ` Andreas Färber 2019-11-23 20:37 ` Andreas Färber [this message] 2019-11-23 20:37 ` [PATCH v4 8/8] ARM: realtek: Enable RTD1195 arch timer Andreas Färber 2019-12-28 14:03 ` [PATCH v4 0/8] ARM: Initial RTD1195 and MeLE X1000 & Horseradish support Andreas Färber 2019-12-28 14:03 ` Andreas Färber
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