From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Subject: [PATCH 11/13] drm/i915/fbc: Start using flip nuke Date: Tue, 26 Nov 2019 19:09:09 +0200 [thread overview] Message-ID: <20191126170911.23253-12-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20191126170911.23253-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> The hardware automagically nukes the cfb on flip. We can use that whenever the plane/crtc configuration doesn't change too much. Let's hook that up. We'll need this for glk+ since we need to introduce an extra vblank wait after FBC disable. As we're currently disabling FBC around all plane updates we'd slow them down by an extra frame. Not a great user experience when your fps is always capped at vrefres/2. With flip nuke we don't need the extra vblank wait. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 50 ++++++++++++++++++------ 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 476733ab0586..b2424b9a369b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -68,7 +68,7 @@ static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc) * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value * we wrote to PIPESRC. */ -static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, +static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache, int *width, int *height) { if (width) @@ -78,7 +78,7 @@ static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, } static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, - struct intel_fbc_state_cache *cache) + const struct intel_fbc_state_cache *cache) { int lines; @@ -827,6 +827,38 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->plane_visible = cache->plane.visible; } +static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct intel_fbc *fbc = &dev_priv->fbc; + const struct intel_fbc_state_cache *cache = &fbc->state_cache; + const struct intel_fbc_reg_params *params = &fbc->params; + + if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) + return false; + + if (!params->plane_visible) + return false; + + if (!intel_fbc_can_activate(crtc)) + return false; + + if (params->fb.format != cache->fb.format) + return false; + + if (params->fb.stride != cache->fb.stride) + return false; + + if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache)) + return false; + + if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride) + return false; + + return true; +} + void intel_fbc_pre_update(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) @@ -846,7 +878,8 @@ void intel_fbc_pre_update(struct intel_crtc *crtc, intel_fbc_update_state_cache(crtc, crtc_state, plane_state); fbc->flip_pending = true; - intel_fbc_deactivate(dev_priv, reason); + if (!intel_fbc_can_flip_nuke(crtc_state)) + intel_fbc_deactivate(dev_priv, reason); unlock: mutex_unlock(&fbc->lock); } @@ -885,7 +918,6 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) return; fbc->flip_pending = false; - WARN_ON(fbc->active); if (!i915_modparams.enable_fbc) { intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); @@ -899,10 +931,9 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) if (!intel_fbc_can_activate(crtc)) return; - if (!fbc->busy_bits) { - intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)"); + if (!fbc->busy_bits) intel_fbc_hw_activate(dev_priv); - } else + else intel_fbc_deactivate(dev_priv, "frontbuffer write"); } @@ -1061,10 +1092,7 @@ void intel_fbc_enable(struct intel_crtc *crtc, mutex_lock(&fbc->lock); if (fbc->crtc) { - if (fbc->crtc == crtc) { - WARN_ON(!crtc_state->enable_fbc); - WARN_ON(fbc->active); - } + WARN_ON(fbc->crtc == crtc && !crtc_state->enable_fbc); goto out; } -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 11/13] drm/i915/fbc: Start using flip nuke Date: Tue, 26 Nov 2019 19:09:09 +0200 [thread overview] Message-ID: <20191126170911.23253-12-ville.syrjala@linux.intel.com> (raw) Message-ID: <20191126170909.qlear5-5SuCFu8HnDsIYao9HMKI12CIW6MjgBeCDM2Q@z> (raw) In-Reply-To: <20191126170911.23253-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> The hardware automagically nukes the cfb on flip. We can use that whenever the plane/crtc configuration doesn't change too much. Let's hook that up. We'll need this for glk+ since we need to introduce an extra vblank wait after FBC disable. As we're currently disabling FBC around all plane updates we'd slow them down by an extra frame. Not a great user experience when your fps is always capped at vrefres/2. With flip nuke we don't need the extra vblank wait. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 50 ++++++++++++++++++------ 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 476733ab0586..b2424b9a369b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -68,7 +68,7 @@ static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc) * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value * we wrote to PIPESRC. */ -static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, +static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache, int *width, int *height) { if (width) @@ -78,7 +78,7 @@ static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, } static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, - struct intel_fbc_state_cache *cache) + const struct intel_fbc_state_cache *cache) { int lines; @@ -827,6 +827,38 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->plane_visible = cache->plane.visible; } +static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct intel_fbc *fbc = &dev_priv->fbc; + const struct intel_fbc_state_cache *cache = &fbc->state_cache; + const struct intel_fbc_reg_params *params = &fbc->params; + + if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) + return false; + + if (!params->plane_visible) + return false; + + if (!intel_fbc_can_activate(crtc)) + return false; + + if (params->fb.format != cache->fb.format) + return false; + + if (params->fb.stride != cache->fb.stride) + return false; + + if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache)) + return false; + + if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride) + return false; + + return true; +} + void intel_fbc_pre_update(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) @@ -846,7 +878,8 @@ void intel_fbc_pre_update(struct intel_crtc *crtc, intel_fbc_update_state_cache(crtc, crtc_state, plane_state); fbc->flip_pending = true; - intel_fbc_deactivate(dev_priv, reason); + if (!intel_fbc_can_flip_nuke(crtc_state)) + intel_fbc_deactivate(dev_priv, reason); unlock: mutex_unlock(&fbc->lock); } @@ -885,7 +918,6 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) return; fbc->flip_pending = false; - WARN_ON(fbc->active); if (!i915_modparams.enable_fbc) { intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); @@ -899,10 +931,9 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) if (!intel_fbc_can_activate(crtc)) return; - if (!fbc->busy_bits) { - intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)"); + if (!fbc->busy_bits) intel_fbc_hw_activate(dev_priv); - } else + else intel_fbc_deactivate(dev_priv, "frontbuffer write"); } @@ -1061,10 +1092,7 @@ void intel_fbc_enable(struct intel_crtc *crtc, mutex_lock(&fbc->lock); if (fbc->crtc) { - if (fbc->crtc == crtc) { - WARN_ON(!crtc_state->enable_fbc); - WARN_ON(fbc->active); - } + WARN_ON(fbc->crtc == crtc && !crtc_state->enable_fbc); goto out; } -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-26 17:09 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-26 17:08 [PATCH 00/13] drm/i915/fbc: Fix FBC for glk+ Ville Syrjala 2019-11-26 17:08 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:08 ` [PATCH 01/13] drm/i915/fbc: Disable fbc by default on all glk+ Ville Syrjala 2019-11-26 17:08 ` [Intel-gfx] " Ville Syrjala 2019-11-28 14:23 ` Sasha Levin 2019-11-28 14:23 ` [Intel-gfx] " Sasha Levin 2019-11-26 17:09 ` [PATCH 02/13] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 03/13] drm/i915: Relocate intel_crtc_active() Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 04/13] drm/i915/fbc: Remove the FBC_RT_BASE setup for ILK/SNB Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 05/13] drm/i915/fbc: Precompute gen9 cfb stride w/a Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:50 ` [PATCH v2 06/14] " Ville Syrjala 2019-11-26 17:50 ` [Intel-gfx] " Ville Syrjala 2019-11-27 11:22 ` [PATCH v3 05/13] " Ville Syrjala 2019-11-27 11:22 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 06/13] drm/i915/fbc: Track plane visibility Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 07/13] drm/i915/fbc: Store fence_id direction in fbc cache/params Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 08/13] drm/i915/fbc: Make fence_id optional for i965gm Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 09/13] drm/i915/fbc: s/gen9 && !glk/gen9_bc || bxt/ Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 10/13] drm/i915/fbc: Nuke fbc.enabled Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` Ville Syrjala [this message] 2019-11-26 17:09 ` [Intel-gfx] [PATCH 11/13] drm/i915/fbc: Start using flip nuke Ville Syrjala 2019-11-26 17:09 ` [PATCH 12/13] drm/i915/fbc: Wait for vblank after FBC disable on glk+ Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 13/13] drm/i915/fbc: Enable fbc by default on glk+ once again Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 21:13 ` ✗ Fi.CI.BAT: failure for drm/i915/fbc: Fix FBC for glk+ Patchwork 2019-11-26 21:13 ` [Intel-gfx] " Patchwork 2019-11-27 7:11 ` [PATCH 00/13] " Daniel Drake 2019-11-27 7:11 ` [Intel-gfx] " Daniel Drake 2019-11-27 16:14 ` ✗ Fi.CI.BUILD: failure for drm/i915/fbc: Fix FBC for glk+ (rev3) Patchwork 2019-11-27 16:14 ` [Intel-gfx] " Patchwork
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