From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/13] drm/i915/fbc: Store fence_id direction in fbc cache/params Date: Tue, 26 Nov 2019 19:09:05 +0200 [thread overview] Message-ID: <20191126170911.23253-8-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20191126170911.23253-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Rather than playing around with vma+flags let's just grab the fence id from within and stash that directly in the fbc cache/params. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 33 +++++++++++++----------- drivers/gpu/drm/i915/i915_drv.h | 8 ++---- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 642074990726..707b9d0cdc9b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -151,7 +151,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) if (IS_I945GM(dev_priv)) fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; - fbc_ctl |= params->vma->fence->id; + fbc_ctl |= params->fence_id; I915_WRITE(FBC_CONTROL, fbc_ctl); } @@ -171,8 +171,8 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv) else dpfc_ctl |= DPFC_CTL_LIMIT_1X; - if (params->flags & PLANE_HAS_FENCE) { - dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id; + if (params->fence_id >= 0) { + dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id; I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); } else { I915_WRITE(DPFC_FENCE_YOFF, 0); @@ -229,14 +229,14 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) break; } - if (params->flags & PLANE_HAS_FENCE) { + if (params->fence_id >= 0) { dpfc_ctl |= DPFC_CTL_FENCE_EN; if (IS_GEN(dev_priv, 5)) - dpfc_ctl |= params->vma->fence->id; + dpfc_ctl |= params->fence_id; if (IS_GEN(dev_priv, 6)) { I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | - params->vma->fence->id); + params->fence_id); I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); } @@ -309,11 +309,11 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) break; } - if (params->flags & PLANE_HAS_FENCE) { + if (params->fence_id >= 0) { dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | - params->vma->fence->id); + params->fence_id); I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); } else { I915_WRITE(SNB_DPFC_CTL_SA,0); @@ -659,10 +659,14 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->fb.format = fb->format; cache->fb.stride = fb->pitches[0]; - cache->vma = plane_state->vma; - cache->flags = plane_state->flags; - if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence)) - cache->flags &= ~PLANE_HAS_FENCE; + WARN_ON(plane_state->flags & PLANE_HAS_FENCE && + !plane_state->vma->fence); + + if (plane_state->flags & PLANE_HAS_FENCE && + plane_state->vma->fence) + cache->fence_id = plane_state->vma->fence->id; + else + cache->fence_id = -1; } static bool intel_fbc_can_activate(struct intel_crtc *crtc) @@ -707,7 +711,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * For now this will effecively disable FBC with 90/270 degree * rotation. */ - if (!(cache->flags & PLANE_HAS_FENCE)) { + if (cache->fence_id < 0) { fbc->no_fbc_reason = "framebuffer not tiled or fenced"; return false; } @@ -804,8 +808,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, * zero. */ memset(params, 0, sizeof(*params)); - params->vma = cache->vma; - params->flags = cache->flags; + params->fence_id = cache->fence_id; params->crtc.pipe = crtc->pipe; params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 06fa8fbd5ae9..852c0204fa0b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -386,9 +386,6 @@ struct intel_fbc { * these problems. */ struct intel_fbc_state_cache { - struct i915_vma *vma; - unsigned long flags; - struct { unsigned int mode_flags; u32 hsw_bdw_pixel_rate; @@ -418,6 +415,7 @@ struct intel_fbc { unsigned int stride; } fb; u16 gen9_wa_cfb_stride; + s8 fence_id; } state_cache; /* @@ -428,9 +426,6 @@ struct intel_fbc { * are supposed to read from it in order to program the registers. */ struct intel_fbc_reg_params { - struct i915_vma *vma; - unsigned long flags; - struct { enum pipe pipe; enum i9xx_plane_id i9xx_plane; @@ -444,6 +439,7 @@ struct intel_fbc { int cfb_size; u16 gen9_wa_cfb_stride; + s8 fence_id; bool plane_visible; } params; -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 07/13] drm/i915/fbc: Store fence_id direction in fbc cache/params Date: Tue, 26 Nov 2019 19:09:05 +0200 [thread overview] Message-ID: <20191126170911.23253-8-ville.syrjala@linux.intel.com> (raw) Message-ID: <20191126170905.08GnO0HSDX8QA8co8TPRZ0w16mSLa2OE9kcpx_1yGlQ@z> (raw) In-Reply-To: <20191126170911.23253-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Rather than playing around with vma+flags let's just grab the fence id from within and stash that directly in the fbc cache/params. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 33 +++++++++++++----------- drivers/gpu/drm/i915/i915_drv.h | 8 ++---- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 642074990726..707b9d0cdc9b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -151,7 +151,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) if (IS_I945GM(dev_priv)) fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; - fbc_ctl |= params->vma->fence->id; + fbc_ctl |= params->fence_id; I915_WRITE(FBC_CONTROL, fbc_ctl); } @@ -171,8 +171,8 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv) else dpfc_ctl |= DPFC_CTL_LIMIT_1X; - if (params->flags & PLANE_HAS_FENCE) { - dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id; + if (params->fence_id >= 0) { + dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id; I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); } else { I915_WRITE(DPFC_FENCE_YOFF, 0); @@ -229,14 +229,14 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) break; } - if (params->flags & PLANE_HAS_FENCE) { + if (params->fence_id >= 0) { dpfc_ctl |= DPFC_CTL_FENCE_EN; if (IS_GEN(dev_priv, 5)) - dpfc_ctl |= params->vma->fence->id; + dpfc_ctl |= params->fence_id; if (IS_GEN(dev_priv, 6)) { I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | - params->vma->fence->id); + params->fence_id); I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); } @@ -309,11 +309,11 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) break; } - if (params->flags & PLANE_HAS_FENCE) { + if (params->fence_id >= 0) { dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | - params->vma->fence->id); + params->fence_id); I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); } else { I915_WRITE(SNB_DPFC_CTL_SA,0); @@ -659,10 +659,14 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->fb.format = fb->format; cache->fb.stride = fb->pitches[0]; - cache->vma = plane_state->vma; - cache->flags = plane_state->flags; - if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence)) - cache->flags &= ~PLANE_HAS_FENCE; + WARN_ON(plane_state->flags & PLANE_HAS_FENCE && + !plane_state->vma->fence); + + if (plane_state->flags & PLANE_HAS_FENCE && + plane_state->vma->fence) + cache->fence_id = plane_state->vma->fence->id; + else + cache->fence_id = -1; } static bool intel_fbc_can_activate(struct intel_crtc *crtc) @@ -707,7 +711,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * For now this will effecively disable FBC with 90/270 degree * rotation. */ - if (!(cache->flags & PLANE_HAS_FENCE)) { + if (cache->fence_id < 0) { fbc->no_fbc_reason = "framebuffer not tiled or fenced"; return false; } @@ -804,8 +808,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, * zero. */ memset(params, 0, sizeof(*params)); - params->vma = cache->vma; - params->flags = cache->flags; + params->fence_id = cache->fence_id; params->crtc.pipe = crtc->pipe; params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 06fa8fbd5ae9..852c0204fa0b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -386,9 +386,6 @@ struct intel_fbc { * these problems. */ struct intel_fbc_state_cache { - struct i915_vma *vma; - unsigned long flags; - struct { unsigned int mode_flags; u32 hsw_bdw_pixel_rate; @@ -418,6 +415,7 @@ struct intel_fbc { unsigned int stride; } fb; u16 gen9_wa_cfb_stride; + s8 fence_id; } state_cache; /* @@ -428,9 +426,6 @@ struct intel_fbc { * are supposed to read from it in order to program the registers. */ struct intel_fbc_reg_params { - struct i915_vma *vma; - unsigned long flags; - struct { enum pipe pipe; enum i9xx_plane_id i9xx_plane; @@ -444,6 +439,7 @@ struct intel_fbc { int cfb_size; u16 gen9_wa_cfb_stride; + s8 fence_id; bool plane_visible; } params; -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-26 17:09 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-26 17:08 [PATCH 00/13] drm/i915/fbc: Fix FBC for glk+ Ville Syrjala 2019-11-26 17:08 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:08 ` [PATCH 01/13] drm/i915/fbc: Disable fbc by default on all glk+ Ville Syrjala 2019-11-26 17:08 ` [Intel-gfx] " Ville Syrjala 2019-11-28 14:23 ` Sasha Levin 2019-11-28 14:23 ` [Intel-gfx] " Sasha Levin 2019-11-26 17:09 ` [PATCH 02/13] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 03/13] drm/i915: Relocate intel_crtc_active() Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 04/13] drm/i915/fbc: Remove the FBC_RT_BASE setup for ILK/SNB Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 05/13] drm/i915/fbc: Precompute gen9 cfb stride w/a Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:50 ` [PATCH v2 06/14] " Ville Syrjala 2019-11-26 17:50 ` [Intel-gfx] " Ville Syrjala 2019-11-27 11:22 ` [PATCH v3 05/13] " Ville Syrjala 2019-11-27 11:22 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 06/13] drm/i915/fbc: Track plane visibility Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` Ville Syrjala [this message] 2019-11-26 17:09 ` [Intel-gfx] [PATCH 07/13] drm/i915/fbc: Store fence_id direction in fbc cache/params Ville Syrjala 2019-11-26 17:09 ` [PATCH 08/13] drm/i915/fbc: Make fence_id optional for i965gm Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 09/13] drm/i915/fbc: s/gen9 && !glk/gen9_bc || bxt/ Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 10/13] drm/i915/fbc: Nuke fbc.enabled Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 11/13] drm/i915/fbc: Start using flip nuke Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 12/13] drm/i915/fbc: Wait for vblank after FBC disable on glk+ Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 17:09 ` [PATCH 13/13] drm/i915/fbc: Enable fbc by default on glk+ once again Ville Syrjala 2019-11-26 17:09 ` [Intel-gfx] " Ville Syrjala 2019-11-26 21:13 ` ✗ Fi.CI.BAT: failure for drm/i915/fbc: Fix FBC for glk+ Patchwork 2019-11-26 21:13 ` [Intel-gfx] " Patchwork 2019-11-27 7:11 ` [PATCH 00/13] " Daniel Drake 2019-11-27 7:11 ` [Intel-gfx] " Daniel Drake 2019-11-27 16:14 ` ✗ Fi.CI.BUILD: failure for drm/i915/fbc: Fix FBC for glk+ (rev3) Patchwork 2019-11-27 16:14 ` [Intel-gfx] " Patchwork
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