From: Alexey Kardashevskiy <aik@ozlabs.ru> To: linuxppc-dev@lists.ozlabs.org Cc: David Gibson <david@gibson.dropbear.id.au>, kvm@vger.kernel.org, Alistair Popple <alistair@popple.id.au>, Alex Williamson <alex.williamson@redhat.com>, Oliver O'Halloran <oohall@gmail.com>, Alexey Kardashevskiy <aik@ozlabs.ru> Subject: [PATCH kernel RFC 2/4] powerpc/powernv/ioda: Allow smaller TCE table levels Date: Mon, 2 Dec 2019 12:59:51 +1100 [thread overview] Message-ID: <20191202015953.127902-3-aik@ozlabs.ru> (raw) In-Reply-To: <20191202015953.127902-1-aik@ozlabs.ru> Now the minimum allocation size for a TCE table level is PAGE_SIZE (64k) as this is the minimum for alloc_pages(). The limit was set in POWER8 where we did not have sparse RAM so we did not need sparse TCE tables. On POWER9 we have gaps in the phys address space for which using multi level TCE tables makes sense. The problem with that is that 64K per level is too much for 2 levels and 1GB pages as it exceeds the hardware limit of 55bits so we need smaller levels. This drops the minimum level size to 4K. For a machine with 2 CPUs, top RAM address 0x4000.0000.0000 (each node gets 32TiB) and 1GiB IOMMU pages: Before the patch: 512KiB or 8 pages. After the patch: 3 pages: one level1 + 2xlevel2 tables, each can map up to 64k>>3<<30 = 8TiB of physical space. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- arch/powerpc/platforms/powernv/pci-ioda-tce.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda-tce.c b/arch/powerpc/platforms/powernv/pci-ioda-tce.c index a0b9c0c23ed2..f9931a5aebe4 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda-tce.c +++ b/arch/powerpc/platforms/powernv/pci-ioda-tce.c @@ -37,7 +37,7 @@ static __be64 *pnv_alloc_tce_level(int nid, unsigned int shift) __be64 *addr; tce_mem = alloc_pages_node(nid, GFP_ATOMIC | __GFP_NOWARN, - shift - PAGE_SHIFT); + shift > PAGE_SHIFT ? shift - PAGE_SHIFT : 0); if (!tce_mem) { pr_err("Failed to allocate a TCE memory, level shift=%d\n", shift); @@ -282,7 +282,7 @@ long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, /* Adjust direct table size from window_size and levels */ entries_shift = (entries_shift + levels - 1) / levels; level_shift = entries_shift + 3; - level_shift = max_t(unsigned int, level_shift, PAGE_SHIFT); + level_shift = max_t(unsigned int, level_shift, 12); /* 4K is minimum */ if ((level_shift - 3) * levels + page_shift >= 55) return -EINVAL; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Kardashevskiy <aik@ozlabs.ru> To: linuxppc-dev@lists.ozlabs.org Cc: kvm@vger.kernel.org, Alexey Kardashevskiy <aik@ozlabs.ru>, Alistair Popple <alistair@popple.id.au>, Alex Williamson <alex.williamson@redhat.com>, Oliver O'Halloran <oohall@gmail.com>, David Gibson <david@gibson.dropbear.id.au> Subject: [PATCH kernel RFC 2/4] powerpc/powernv/ioda: Allow smaller TCE table levels Date: Mon, 2 Dec 2019 12:59:51 +1100 [thread overview] Message-ID: <20191202015953.127902-3-aik@ozlabs.ru> (raw) In-Reply-To: <20191202015953.127902-1-aik@ozlabs.ru> Now the minimum allocation size for a TCE table level is PAGE_SIZE (64k) as this is the minimum for alloc_pages(). The limit was set in POWER8 where we did not have sparse RAM so we did not need sparse TCE tables. On POWER9 we have gaps in the phys address space for which using multi level TCE tables makes sense. The problem with that is that 64K per level is too much for 2 levels and 1GB pages as it exceeds the hardware limit of 55bits so we need smaller levels. This drops the minimum level size to 4K. For a machine with 2 CPUs, top RAM address 0x4000.0000.0000 (each node gets 32TiB) and 1GiB IOMMU pages: Before the patch: 512KiB or 8 pages. After the patch: 3 pages: one level1 + 2xlevel2 tables, each can map up to 64k>>3<<30 = 8TiB of physical space. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- arch/powerpc/platforms/powernv/pci-ioda-tce.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda-tce.c b/arch/powerpc/platforms/powernv/pci-ioda-tce.c index a0b9c0c23ed2..f9931a5aebe4 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda-tce.c +++ b/arch/powerpc/platforms/powernv/pci-ioda-tce.c @@ -37,7 +37,7 @@ static __be64 *pnv_alloc_tce_level(int nid, unsigned int shift) __be64 *addr; tce_mem = alloc_pages_node(nid, GFP_ATOMIC | __GFP_NOWARN, - shift - PAGE_SHIFT); + shift > PAGE_SHIFT ? shift - PAGE_SHIFT : 0); if (!tce_mem) { pr_err("Failed to allocate a TCE memory, level shift=%d\n", shift); @@ -282,7 +282,7 @@ long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, /* Adjust direct table size from window_size and levels */ entries_shift = (entries_shift + levels - 1) / levels; level_shift = entries_shift + 3; - level_shift = max_t(unsigned int, level_shift, PAGE_SHIFT); + level_shift = max_t(unsigned int, level_shift, 12); /* 4K is minimum */ if ((level_shift - 3) * levels + page_shift >= 55) return -EINVAL; -- 2.17.1
next prev parent reply other threads:[~2019-12-02 2:09 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-02 1:59 [PATCH kernel RFC 0/4] powerpc/powenv/ioda: Allow huge DMA window at 4GB Alexey Kardashevskiy 2019-12-02 1:59 ` Alexey Kardashevskiy 2019-12-02 1:59 ` [PATCH kernel RFC 1/4] powerpc/powernv/ioda: Rework for " Alexey Kardashevskiy 2019-12-02 1:59 ` Alexey Kardashevskiy 2019-12-02 1:59 ` Alexey Kardashevskiy [this message] 2019-12-02 1:59 ` [PATCH kernel RFC 2/4] powerpc/powernv/ioda: Allow smaller TCE table levels Alexey Kardashevskiy 2019-12-02 1:59 ` [PATCH kernel RFC 3/4] powerpc/powernv/phb4: Add 4GB IOMMU bypass mode Alexey Kardashevskiy 2019-12-02 1:59 ` Alexey Kardashevskiy 2019-12-02 1:59 ` [PATCH kernel RFC 4/4] vfio/spapr_tce: Advertise and allow a huge DMA windows at 4GB Alexey Kardashevskiy 2019-12-02 1:59 ` Alexey Kardashevskiy 2019-12-02 5:36 ` [PATCH kernel RFC 0/4] powerpc/powenv/ioda: Allow huge DMA window " Alistair Popple 2019-12-02 5:36 ` Alistair Popple 2019-12-02 5:58 ` Alexey Kardashevskiy 2019-12-02 5:58 ` Alexey Kardashevskiy 2019-12-02 5:51 ` [PATCH kernel RFC 00/4] powerpc/powernv/ioda: Move TCE bypass base to PE Alexey Kardashevskiy 2019-12-02 5:51 ` Alexey Kardashevskiy 2020-01-10 4:18 ` [PATCH kernel RFC 0/4] powerpc/powenv/ioda: Allow huge DMA window at 4GB Alexey Kardashevskiy 2020-01-10 4:18 ` Alexey Kardashevskiy 2020-01-23 0:53 ` Alexey Kardashevskiy 2020-01-23 0:53 ` Alexey Kardashevskiy 2020-01-23 1:17 ` David Gibson 2020-01-23 1:17 ` David Gibson 2020-01-23 8:42 ` Alexey Kardashevskiy 2020-01-23 8:42 ` Alexey Kardashevskiy
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20191202015953.127902-3-aik@ozlabs.ru \ --to=aik@ozlabs.ru \ --cc=alex.williamson@redhat.com \ --cc=alistair@popple.id.au \ --cc=david@gibson.dropbear.id.au \ --cc=kvm@vger.kernel.org \ --cc=linuxppc-dev@lists.ozlabs.org \ --cc=oohall@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.