From: <Tudor.Ambarus@microchip.com> To: <herbert@gondor.apana.org.au> Cc: <Nicolas.Ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <Ludovic.Desroches@microchip.com>, <linux-crypto@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <Tudor.Ambarus@microchip.com> Subject: [PATCH 11/16] crypto: atmel-aes - Fix counter overflow in CTR mode Date: Thu, 5 Dec 2019 09:54:01 +0000 [thread overview] Message-ID: <20191205095326.5094-12-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20191205095326.5094-1-tudor.ambarus@microchip.com> From: Tudor Ambarus <tudor.ambarus@microchip.com> 32 bit counter is not supported by neither of our AES IPs, all implement a 16 bit block counter. Drop the 32 bit block counter logic. Fixes: fcac83656a3e ("crypto: atmel-aes - fix the counter overflow in CTR mode") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/crypto/atmel-aes.c | 37 ++++++++++++------------------------- 1 file changed, 12 insertions(+), 25 deletions(-) diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c index d7e28ec456ff..cbfe6ccd2a0d 100644 --- a/drivers/crypto/atmel-aes.c +++ b/drivers/crypto/atmel-aes.c @@ -89,7 +89,6 @@ struct atmel_aes_caps { bool has_dualbuff; bool has_cfb64; - bool has_ctr32; bool has_gcm; bool has_xts; bool has_authenc; @@ -1019,8 +1018,9 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); struct skcipher_request *req = skcipher_request_cast(dd->areq); struct scatterlist *src, *dst; - u32 ctr, blocks; size_t datalen; + u32 ctr; + u16 blocks, start, end; bool use_dma, fragmented = false; /* Check for transfer completion. */ @@ -1032,27 +1032,17 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) datalen = req->cryptlen - ctx->offset; blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE); ctr = be32_to_cpu(ctx->iv[3]); - if (dd->caps.has_ctr32) { - /* Check 32bit counter overflow. */ - u32 start = ctr; - u32 end = start + blocks - 1; - - if (end < start) { - ctr |= 0xffffffff; - datalen = AES_BLOCK_SIZE * -start; - fragmented = true; - } - } else { - /* Check 16bit counter overflow. */ - u16 start = ctr & 0xffff; - u16 end = start + (u16)blocks - 1; - - if (blocks >> 16 || end < start) { - ctr |= 0xffff; - datalen = AES_BLOCK_SIZE * (0x10000-start); - fragmented = true; - } + + /* Check 16bit counter overflow. */ + start = ctr & 0xffff; + end = start + blocks - 1; + + if (blocks >> 16 || end < start) { + ctr |= 0xffff; + datalen = AES_BLOCK_SIZE * (0x10000 - start); + fragmented = true; } + use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD); /* Jump to offset. */ @@ -2538,7 +2528,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) { dd->caps.has_dualbuff = 0; dd->caps.has_cfb64 = 0; - dd->caps.has_ctr32 = 0; dd->caps.has_gcm = 0; dd->caps.has_xts = 0; dd->caps.has_authenc = 0; @@ -2549,7 +2538,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) case 0x500: dd->caps.has_dualbuff = 1; dd->caps.has_cfb64 = 1; - dd->caps.has_ctr32 = 1; dd->caps.has_gcm = 1; dd->caps.has_xts = 1; dd->caps.has_authenc = 1; @@ -2558,7 +2546,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) case 0x200: dd->caps.has_dualbuff = 1; dd->caps.has_cfb64 = 1; - dd->caps.has_ctr32 = 1; dd->caps.has_gcm = 1; dd->caps.max_burst_size = 4; break; -- 2.14.5
WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com> To: <herbert@gondor.apana.org.au> Cc: alexandre.belloni@bootlin.com, Tudor.Ambarus@microchip.com, linux-kernel@vger.kernel.org, Ludovic.Desroches@microchip.com, linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 11/16] crypto: atmel-aes - Fix counter overflow in CTR mode Date: Thu, 5 Dec 2019 09:54:01 +0000 [thread overview] Message-ID: <20191205095326.5094-12-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20191205095326.5094-1-tudor.ambarus@microchip.com> From: Tudor Ambarus <tudor.ambarus@microchip.com> 32 bit counter is not supported by neither of our AES IPs, all implement a 16 bit block counter. Drop the 32 bit block counter logic. Fixes: fcac83656a3e ("crypto: atmel-aes - fix the counter overflow in CTR mode") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/crypto/atmel-aes.c | 37 ++++++++++++------------------------- 1 file changed, 12 insertions(+), 25 deletions(-) diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c index d7e28ec456ff..cbfe6ccd2a0d 100644 --- a/drivers/crypto/atmel-aes.c +++ b/drivers/crypto/atmel-aes.c @@ -89,7 +89,6 @@ struct atmel_aes_caps { bool has_dualbuff; bool has_cfb64; - bool has_ctr32; bool has_gcm; bool has_xts; bool has_authenc; @@ -1019,8 +1018,9 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); struct skcipher_request *req = skcipher_request_cast(dd->areq); struct scatterlist *src, *dst; - u32 ctr, blocks; size_t datalen; + u32 ctr; + u16 blocks, start, end; bool use_dma, fragmented = false; /* Check for transfer completion. */ @@ -1032,27 +1032,17 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) datalen = req->cryptlen - ctx->offset; blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE); ctr = be32_to_cpu(ctx->iv[3]); - if (dd->caps.has_ctr32) { - /* Check 32bit counter overflow. */ - u32 start = ctr; - u32 end = start + blocks - 1; - - if (end < start) { - ctr |= 0xffffffff; - datalen = AES_BLOCK_SIZE * -start; - fragmented = true; - } - } else { - /* Check 16bit counter overflow. */ - u16 start = ctr & 0xffff; - u16 end = start + (u16)blocks - 1; - - if (blocks >> 16 || end < start) { - ctr |= 0xffff; - datalen = AES_BLOCK_SIZE * (0x10000-start); - fragmented = true; - } + + /* Check 16bit counter overflow. */ + start = ctr & 0xffff; + end = start + blocks - 1; + + if (blocks >> 16 || end < start) { + ctr |= 0xffff; + datalen = AES_BLOCK_SIZE * (0x10000 - start); + fragmented = true; } + use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD); /* Jump to offset. */ @@ -2538,7 +2528,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) { dd->caps.has_dualbuff = 0; dd->caps.has_cfb64 = 0; - dd->caps.has_ctr32 = 0; dd->caps.has_gcm = 0; dd->caps.has_xts = 0; dd->caps.has_authenc = 0; @@ -2549,7 +2538,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) case 0x500: dd->caps.has_dualbuff = 1; dd->caps.has_cfb64 = 1; - dd->caps.has_ctr32 = 1; dd->caps.has_gcm = 1; dd->caps.has_xts = 1; dd->caps.has_authenc = 1; @@ -2558,7 +2546,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) case 0x200: dd->caps.has_dualbuff = 1; dd->caps.has_cfb64 = 1; - dd->caps.has_ctr32 = 1; dd->caps.has_gcm = 1; dd->caps.max_burst_size = 4; break; -- 2.14.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-12-05 9:54 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-05 9:53 [PATCH 00/16] crypto: atmel - Fixes and cleanup patches Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 01/16] crypto: atmel-tdes: Constify value to write to hw Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 02/16] crypto: atmel-{sha,tdes} - Change algorithm priorities Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 03/16] crypto: atmel-tdes - Remove unused header includes Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 04/16] crypto: atmel-{sha,tdes} - Propagate error from _hw_version_init() Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 05/16] crypto: atmel-{aes,sha,tdes} - Drop superfluous error message in probe() Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 06/16] crypto: atmel-{aes,sha,tdes} - Rename labels " Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 06/16] crypto: atmel-{aes, sha, tdes} " Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 07/16] crypto: atmel-tdes - Remove useless write in Control Register Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 08/16] crypto: atmel-tdes - Map driver data flags to Mode Register Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:53 ` [PATCH 09/16] crypto: atmel-tdes - Drop unnecessary passing of tfm Tudor.Ambarus 2019-12-05 9:53 ` Tudor.Ambarus 2019-12-05 9:54 ` [PATCH 10/16] crypto: atmel-{aes,tdes} - Do not save IV for ECB mode Tudor.Ambarus 2019-12-05 9:54 ` Tudor.Ambarus 2019-12-05 9:54 ` Tudor.Ambarus [this message] 2019-12-05 9:54 ` [PATCH 11/16] crypto: atmel-aes - Fix counter overflow in CTR mode Tudor.Ambarus 2019-12-05 9:54 ` [PATCH 12/16] crypto: atmel-aes - Fix saving of IV for " Tudor.Ambarus 2019-12-05 9:54 ` Tudor.Ambarus 2019-12-05 9:54 ` [PATCH 13/16] crypto: atmel-{sha,tdes} - Remove unused 'err' member of driver data Tudor.Ambarus 2019-12-05 9:54 ` Tudor.Ambarus 2019-12-05 9:54 ` [PATCH 14/16] crypto: atmel-sha - Void return type for atmel_sha_update_dma_stop() Tudor.Ambarus 2019-12-05 9:54 ` Tudor.Ambarus 2019-12-05 9:54 ` [PATCH 15/16] crypto: atmel-aes - Use gcm helper to check authsize Tudor.Ambarus 2019-12-05 9:54 ` Tudor.Ambarus 2019-12-05 9:54 ` [PATCH 16/16] crypto: atmel-{aes,sha,tdes} - Group common alg type init in dedicated methods Tudor.Ambarus 2019-12-05 9:54 ` Tudor.Ambarus 2019-12-05 13:48 ` [PATCH v2 " Tudor.Ambarus 2019-12-05 13:48 ` [PATCH v2 16/16] crypto: atmel-{aes, sha, tdes} " Tudor.Ambarus 2019-12-11 9:45 ` [PATCH 00/16] crypto: atmel - Fixes and cleanup patches Herbert Xu 2019-12-11 9:45 ` Herbert Xu
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