From: Douglas Anderson <dianders@chromium.org> To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com> Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, seanpaul@chromium.org, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Douglas Anderson <dianders@chromium.org>, Rob Clark <robdclark@gmail.com>, Jonas Karlman <jonas@kwiboo.se>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie <airlied@linux.ie>, Jernej Skrabec <jernej.skrabec@siol.net>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Subject: [PATCH v2 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Date: Tue, 17 Dec 2019 16:47:39 -0800 [thread overview] Message-ID: <20191217164702.v2.7.I1fc75ad11db9048ef08cfe1ab7322753d9a219c7@changeid> (raw) In-Reply-To: <20191218004741.102067-1-dianders@chromium.org> We'll re-organize the ti_sn_bridge_enable() function a bit to group together all the parts relating to link training and split them into a sub-function. This is not intended to have any functional change and is in preparation for trying link training several times at different rates. One small side effect here is that if link training fails we'll now leave the DP PLL disabled, but that seems like a sane thing to do. Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Rob Clark <robdclark@gmail.com> --- Changes in v2: None drivers/gpu/drm/bridge/ti-sn65dsi86.c | 86 ++++++++++++++++----------- 1 file changed, 52 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index d5990a0947b9..48fb4dc72e1c 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -530,6 +530,46 @@ static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) return data & DP_LANE_COUNT_MASK; } +static int ti_sn_link_training(struct ti_sn_bridge *pdata) +{ + unsigned int val; + int ret; + + /* set dp clk frequency value */ + ti_sn_bridge_set_dp_rate(pdata); + + /* enable DP PLL */ + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); + + ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, + val & DPPLL_SRC_DP_PLL_LOCK, 1000, + 50 * 1000); + if (ret) { + DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret); + goto exit; + } + + /* Semi auto link training mode */ + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); + ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, + val == ML_TX_MAIN_LINK_OFF || + val == ML_TX_NORMAL_MODE, 1000, + 500 * 1000); + if (ret) { + DRM_ERROR("Training complete polling failed (%d)\n", ret); + } else if (val == ML_TX_MAIN_LINK_OFF) { + DRM_ERROR("Link training failed, link is off\n"); + ret = -EIO; + } + +exit: + /* Disable the PLL if we failed */ + if (ret) + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); + + return ret; +} + static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); @@ -555,29 +595,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, CHA_DSI_LANES_MASK, val); - /* Set the DP output format (18 bpp or 24 bpp) */ - val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; - regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); - - /* DP lane config */ - val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); - regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, - val); - - /* set dsi/dp clk frequency value */ + /* set dsi clk frequency value */ ti_sn_bridge_set_dsi_rate(pdata); - ti_sn_bridge_set_dp_rate(pdata); - - /* enable DP PLL */ - regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); - - ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, - val & DPPLL_SRC_DP_PLL_LOCK, 1000, - 50 * 1000); - if (ret) { - DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret); - return; - } /** * The SN65DSI86 only supports ASSR Display Authentication method and @@ -588,19 +607,18 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); - /* Semi auto link training mode */ - regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); - ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, - val == ML_TX_MAIN_LINK_OFF || - val == ML_TX_NORMAL_MODE, 1000, - 500 * 1000); - if (ret) { - DRM_ERROR("Training complete polling failed (%d)\n", ret); - return; - } else if (val == ML_TX_MAIN_LINK_OFF) { - DRM_ERROR("Link training failed, link is off\n"); + /* Set the DP output format (18 bpp or 24 bpp) */ + val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; + regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); + + /* DP lane config */ + val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, + val); + + ret = ti_sn_link_training(pdata); + if (ret) return; - } /* config video parameters */ ti_sn_bridge_set_video_timings(pdata); -- 2.24.1.735.g03f4e72817-goog
WARNING: multiple messages have this Message-ID (diff)
From: Douglas Anderson <dianders@chromium.org> To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com> Cc: robdclark@chromium.org, Jernej Skrabec <jernej.skrabec@siol.net>, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>, David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, Jonas Karlman <jonas@kwiboo.se>, Douglas Anderson <dianders@chromium.org>, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, seanpaul@chromium.org, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Date: Tue, 17 Dec 2019 16:47:39 -0800 [thread overview] Message-ID: <20191217164702.v2.7.I1fc75ad11db9048ef08cfe1ab7322753d9a219c7@changeid> (raw) In-Reply-To: <20191218004741.102067-1-dianders@chromium.org> We'll re-organize the ti_sn_bridge_enable() function a bit to group together all the parts relating to link training and split them into a sub-function. This is not intended to have any functional change and is in preparation for trying link training several times at different rates. One small side effect here is that if link training fails we'll now leave the DP PLL disabled, but that seems like a sane thing to do. Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Rob Clark <robdclark@gmail.com> --- Changes in v2: None drivers/gpu/drm/bridge/ti-sn65dsi86.c | 86 ++++++++++++++++----------- 1 file changed, 52 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index d5990a0947b9..48fb4dc72e1c 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -530,6 +530,46 @@ static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) return data & DP_LANE_COUNT_MASK; } +static int ti_sn_link_training(struct ti_sn_bridge *pdata) +{ + unsigned int val; + int ret; + + /* set dp clk frequency value */ + ti_sn_bridge_set_dp_rate(pdata); + + /* enable DP PLL */ + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); + + ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, + val & DPPLL_SRC_DP_PLL_LOCK, 1000, + 50 * 1000); + if (ret) { + DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret); + goto exit; + } + + /* Semi auto link training mode */ + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); + ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, + val == ML_TX_MAIN_LINK_OFF || + val == ML_TX_NORMAL_MODE, 1000, + 500 * 1000); + if (ret) { + DRM_ERROR("Training complete polling failed (%d)\n", ret); + } else if (val == ML_TX_MAIN_LINK_OFF) { + DRM_ERROR("Link training failed, link is off\n"); + ret = -EIO; + } + +exit: + /* Disable the PLL if we failed */ + if (ret) + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); + + return ret; +} + static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); @@ -555,29 +595,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, CHA_DSI_LANES_MASK, val); - /* Set the DP output format (18 bpp or 24 bpp) */ - val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; - regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); - - /* DP lane config */ - val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); - regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, - val); - - /* set dsi/dp clk frequency value */ + /* set dsi clk frequency value */ ti_sn_bridge_set_dsi_rate(pdata); - ti_sn_bridge_set_dp_rate(pdata); - - /* enable DP PLL */ - regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); - - ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, - val & DPPLL_SRC_DP_PLL_LOCK, 1000, - 50 * 1000); - if (ret) { - DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret); - return; - } /** * The SN65DSI86 only supports ASSR Display Authentication method and @@ -588,19 +607,18 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); - /* Semi auto link training mode */ - regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); - ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, - val == ML_TX_MAIN_LINK_OFF || - val == ML_TX_NORMAL_MODE, 1000, - 500 * 1000); - if (ret) { - DRM_ERROR("Training complete polling failed (%d)\n", ret); - return; - } else if (val == ML_TX_MAIN_LINK_OFF) { - DRM_ERROR("Link training failed, link is off\n"); + /* Set the DP output format (18 bpp or 24 bpp) */ + val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; + regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); + + /* DP lane config */ + val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, + val); + + ret = ti_sn_link_training(pdata); + if (ret) return; - } /* config video parameters */ ti_sn_bridge_set_video_timings(pdata); -- 2.24.1.735.g03f4e72817-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2019-12-18 0:48 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-18 0:47 [PATCH v2 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson [this message] 2019-12-18 0:47 ` [PATCH v2 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 4:01 ` Rob Clark 2019-12-18 4:01 ` Rob Clark 2019-12-18 4:03 ` Rob Clark 2019-12-18 4:03 ` Rob Clark 2019-12-18 22:41 ` Doug Anderson 2019-12-18 22:41 ` Doug Anderson 2019-12-21 13:56 ` kbuild test robot 2019-12-21 13:56 ` kbuild test robot 2019-12-21 13:56 ` kbuild test robot 2020-01-06 22:43 ` Doug Anderson 2020-01-06 22:43 ` Doug Anderson 2020-01-06 22:43 ` Doug Anderson 2020-01-07 0:55 ` [kbuild-all] " Rong Chen 2020-01-07 0:55 ` Rong Chen 2020-01-07 0:55 ` [kbuild-all] " Rong Chen
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