From: Douglas Anderson <dianders@chromium.org> To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com> Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, seanpaul@chromium.org, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Douglas Anderson <dianders@chromium.org>, Jonas Karlman <jonas@kwiboo.se>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie <airlied@linux.ie>, Jernej Skrabec <jernej.skrabec@siol.net>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Subject: [PATCH v2 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Date: Tue, 17 Dec 2019 16:47:41 -0800 [thread overview] Message-ID: <20191217164702.v2.9.Ib59207b66db377380d13748752d6fce5596462c5@changeid> (raw) In-Reply-To: <20191218004741.102067-1-dianders@chromium.org> Based on work by Bjorn Andersson <bjorn.andersson@linaro.org>, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>, and Rob Clark <robdclark@chromium.org>. Let's read the SUPPORTED_LINK_RATES and/or MAX_LINK_RATE (depending on the eDP version of the sink) to figure out what eDP rates are supported and pick the ideal one. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- Changes in v2: - Patch ("Avoid invalid rates") replaces ("Skip non-standard DP rates") drivers/gpu/drm/bridge/ti-sn65dsi86.c | 118 ++++++++++++++++++++------ 1 file changed, 93 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index e1b817ccd9c7..da5ddf6be92b 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -475,39 +475,103 @@ static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata) return i; } -static int ti_sn_bridge_get_max_dp_rate_idx(struct ti_sn_bridge *pdata) +static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata, + bool rate_valid[]) { - u8 data; + u8 dpcd_val; + int rate_times_200khz; int ret; + int i; - ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &data); + ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); + if (ret != 1) { + DRM_DEV_ERROR(pdata->dev, + "Can't read eDP rev (%d), assuming 1.1\n", ret); + dpcd_val = DP_EDP_11; + } + + if (dpcd_val >= DP_EDP_14) { + /* eDP 1.4 devices must provide a custom table */ + __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; + + ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, + sink_rates, sizeof(sink_rates)); + + if (ret != sizeof(sink_rates)) { + DRM_DEV_ERROR(pdata->dev, + "Can't read supported rate table (%d)\n", ret); + + /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ + memset(sink_rates, 0, sizeof(sink_rates)); + } + + for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { + rate_times_200khz = le16_to_cpu(sink_rates[i]); + + if (!rate_times_200khz) + break; + + switch (rate_times_200khz) { + case 27000: + rate_valid[7] = 1; + break; + case 21600: + rate_valid[6] = 1; + break; + case 16200: + rate_valid[5] = 1; + break; + case 13500: + rate_valid[4] = 1; + break; + case 12150: + rate_valid[3] = 1; + break; + case 10800: + rate_valid[2] = 1; + break; + case 8100: + rate_valid[1] = 1; + break; + default: + /* unsupported */ + break; + } + } + + for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { + if (rate_valid[i]) + return; + } + DRM_DEV_ERROR(pdata->dev, + "No matching eDP rates in table; falling back\n"); + } + + /* On older versions best we can do is use DP_MAX_LINK_RATE */ + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); if (ret != 1) { DRM_DEV_ERROR(pdata->dev, "Can't read max rate (%d); assuming 5.4 GHz\n", ret); - return ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; + dpcd_val = DP_LINK_BW_5_4; } - /* - * Return an index into ti_sn_bridge_dp_rate_lut. Just hardcode - * these indicies since it's not like the register spec is ever going - * to change and a loop would just be more complicated. Apparently - * the DP sink can only return these few rates as supported even - * though the bridge allows some rates in between. - */ - switch (data) { - case DP_LINK_BW_1_62: - return 1; - case DP_LINK_BW_2_7: - return 4; + switch (dpcd_val) { + default: + DRM_DEV_ERROR(pdata->dev, + "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); + /* fall through */ case DP_LINK_BW_5_4: - return 7; + rate_valid[7] = 1; + /* fall through */ + case DP_LINK_BW_2_7: + rate_valid[4] = 1; + /* fall through */ + case DP_LINK_BW_1_62: + rate_valid[1] = 1; + break; } - - DRM_DEV_ERROR(pdata->dev, - "Unexpected max data rate (%#x); assuming 5.4 GHz\n", - (int)data); - return ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; } static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) @@ -609,9 +673,9 @@ static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx, static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); + bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)]; const char *last_err_str = "No supported DP rate"; int dp_rate_idx; - int max_dp_rate_idx; unsigned int val; int ret = -EINVAL; @@ -655,11 +719,15 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, val); + ti_sn_bridge_read_valid_rates(pdata, rate_valid); + /* Train until we run out of rates */ - max_dp_rate_idx = ti_sn_bridge_get_max_dp_rate_idx(pdata); for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata); - dp_rate_idx <= max_dp_rate_idx; + dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); dp_rate_idx++) { + if (!rate_valid[dp_rate_idx]) + continue; + ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); if (!ret) break; -- 2.24.1.735.g03f4e72817-goog
WARNING: multiple messages have this Message-ID (diff)
From: Douglas Anderson <dianders@chromium.org> To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com> Cc: robdclark@chromium.org, Jernej Skrabec <jernej.skrabec@siol.net>, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>, David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, Jonas Karlman <jonas@kwiboo.se>, Douglas Anderson <dianders@chromium.org>, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, seanpaul@chromium.org, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, linux-kernel@vger.kernel.org Subject: [PATCH v2 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Date: Tue, 17 Dec 2019 16:47:41 -0800 [thread overview] Message-ID: <20191217164702.v2.9.Ib59207b66db377380d13748752d6fce5596462c5@changeid> (raw) In-Reply-To: <20191218004741.102067-1-dianders@chromium.org> Based on work by Bjorn Andersson <bjorn.andersson@linaro.org>, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>, and Rob Clark <robdclark@chromium.org>. Let's read the SUPPORTED_LINK_RATES and/or MAX_LINK_RATE (depending on the eDP version of the sink) to figure out what eDP rates are supported and pick the ideal one. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- Changes in v2: - Patch ("Avoid invalid rates") replaces ("Skip non-standard DP rates") drivers/gpu/drm/bridge/ti-sn65dsi86.c | 118 ++++++++++++++++++++------ 1 file changed, 93 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index e1b817ccd9c7..da5ddf6be92b 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -475,39 +475,103 @@ static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata) return i; } -static int ti_sn_bridge_get_max_dp_rate_idx(struct ti_sn_bridge *pdata) +static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata, + bool rate_valid[]) { - u8 data; + u8 dpcd_val; + int rate_times_200khz; int ret; + int i; - ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &data); + ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); + if (ret != 1) { + DRM_DEV_ERROR(pdata->dev, + "Can't read eDP rev (%d), assuming 1.1\n", ret); + dpcd_val = DP_EDP_11; + } + + if (dpcd_val >= DP_EDP_14) { + /* eDP 1.4 devices must provide a custom table */ + __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; + + ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, + sink_rates, sizeof(sink_rates)); + + if (ret != sizeof(sink_rates)) { + DRM_DEV_ERROR(pdata->dev, + "Can't read supported rate table (%d)\n", ret); + + /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ + memset(sink_rates, 0, sizeof(sink_rates)); + } + + for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { + rate_times_200khz = le16_to_cpu(sink_rates[i]); + + if (!rate_times_200khz) + break; + + switch (rate_times_200khz) { + case 27000: + rate_valid[7] = 1; + break; + case 21600: + rate_valid[6] = 1; + break; + case 16200: + rate_valid[5] = 1; + break; + case 13500: + rate_valid[4] = 1; + break; + case 12150: + rate_valid[3] = 1; + break; + case 10800: + rate_valid[2] = 1; + break; + case 8100: + rate_valid[1] = 1; + break; + default: + /* unsupported */ + break; + } + } + + for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { + if (rate_valid[i]) + return; + } + DRM_DEV_ERROR(pdata->dev, + "No matching eDP rates in table; falling back\n"); + } + + /* On older versions best we can do is use DP_MAX_LINK_RATE */ + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); if (ret != 1) { DRM_DEV_ERROR(pdata->dev, "Can't read max rate (%d); assuming 5.4 GHz\n", ret); - return ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; + dpcd_val = DP_LINK_BW_5_4; } - /* - * Return an index into ti_sn_bridge_dp_rate_lut. Just hardcode - * these indicies since it's not like the register spec is ever going - * to change and a loop would just be more complicated. Apparently - * the DP sink can only return these few rates as supported even - * though the bridge allows some rates in between. - */ - switch (data) { - case DP_LINK_BW_1_62: - return 1; - case DP_LINK_BW_2_7: - return 4; + switch (dpcd_val) { + default: + DRM_DEV_ERROR(pdata->dev, + "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); + /* fall through */ case DP_LINK_BW_5_4: - return 7; + rate_valid[7] = 1; + /* fall through */ + case DP_LINK_BW_2_7: + rate_valid[4] = 1; + /* fall through */ + case DP_LINK_BW_1_62: + rate_valid[1] = 1; + break; } - - DRM_DEV_ERROR(pdata->dev, - "Unexpected max data rate (%#x); assuming 5.4 GHz\n", - (int)data); - return ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; } static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) @@ -609,9 +673,9 @@ static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx, static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); + bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)]; const char *last_err_str = "No supported DP rate"; int dp_rate_idx; - int max_dp_rate_idx; unsigned int val; int ret = -EINVAL; @@ -655,11 +719,15 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, val); + ti_sn_bridge_read_valid_rates(pdata, rate_valid); + /* Train until we run out of rates */ - max_dp_rate_idx = ti_sn_bridge_get_max_dp_rate_idx(pdata); for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata); - dp_rate_idx <= max_dp_rate_idx; + dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); dp_rate_idx++) { + if (!rate_valid[dp_rate_idx]) + continue; + ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); if (!ret) break; -- 2.24.1.735.g03f4e72817-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2019-12-18 0:48 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-18 0:47 [PATCH v2 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` [PATCH v2 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson 2019-12-18 0:47 ` Douglas Anderson [this message] 2019-12-18 0:47 ` [PATCH v2 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Douglas Anderson 2019-12-18 4:01 ` Rob Clark 2019-12-18 4:01 ` Rob Clark 2019-12-18 4:03 ` Rob Clark 2019-12-18 4:03 ` Rob Clark 2019-12-18 22:41 ` Doug Anderson 2019-12-18 22:41 ` Doug Anderson 2019-12-21 13:56 ` kbuild test robot 2019-12-21 13:56 ` kbuild test robot 2019-12-21 13:56 ` kbuild test robot 2020-01-06 22:43 ` Doug Anderson 2020-01-06 22:43 ` Doug Anderson 2020-01-06 22:43 ` Doug Anderson 2020-01-07 0:55 ` [kbuild-all] " Rong Chen 2020-01-07 0:55 ` Rong Chen 2020-01-07 0:55 ` [kbuild-all] " Rong Chen
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