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From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>
Cc: <iommu@lists.linux-foundation.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>, <wsd_upstream@mediatek.com>,
	Chao Hao <chao.hao@mediatek.com>, Jun Yan <jun.yan@mediatek.com>,
	Cui Zhang <zhang.cui@mediatek.com>,
	Yong Wu <yong.wu@mediatek.com>, Anan Sun <anan.sun@mediatek.com>
Subject: [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779
Date: Sun, 5 Jan 2020 18:45:11 +0800	[thread overview]
Message-ID: <20200105104523.31006-8-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com>

When some platforms(ex:later mt6779) define has_wr_len variable,
we need to set REG_MMU_WR_LEN to improve performance. So we add
REG_MMU_WR_LEN register define in this patch.

Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 11 +++++++++++
 drivers/iommu/mtk_iommu.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5de13ab1094e..ad5690350d6a 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -44,6 +44,8 @@
 
 #define REG_MMU_MISC_CTRL			0x048
 #define REG_MMU_DCM_DIS				0x050
+#define REG_MMU_WR_LEN				0x054
+#define F_MMU_WR_THROT_DIS			(BIT(5) |  BIT(21))
 
 #define REG_MMU_CTRL_REG			0x110
 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR		(2 << 4)
@@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 	}
 	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 
+	if (data->plat_data->has_wr_len) {
+		/* write command throttling mode */
+		regval = readl_relaxed(data->base + REG_MMU_WR_LEN);
+		regval &= ~F_MMU_WR_THROT_DIS;
+		writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
+	}
+
 	if (data->plat_data->reset_axi)
 		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
 
@@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 	struct mtk_iommu_suspend_reg *reg = &data->reg;
 	void __iomem *base = data->base;
 
+	reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN);
 	reg->standard_axi_mode = readl_relaxed(base +
 					       REG_MMU_MISC_CTRL);
 	reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
@@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
 		dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
 		return ret;
 	}
+	writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN);
 	writel_relaxed(reg->standard_axi_mode,
 		       base + REG_MMU_MISC_CTRL);
 	writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index d4495230c6e7..0623f199e96f 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg {
 	u32				int_main_control;
 	u32				ivrp_paddr;
 	u32				vld_pa_rng;
+	u32				wr_len;
 };
 
 enum mtk_iommu_plat {
@@ -43,6 +44,7 @@ struct mtk_iommu_plat_data {
 	bool                has_sub_comm[2];
 	bool                has_vld_pa_rng;
 	bool                reset_axi;
+	bool                has_wr_len;
 	u32                 m4u1_mask;
 	u32                 inv_sel_reg;
 	unsigned char       larbid_remap[2][MTK_LARB_NR_MAX];
-- 
2.18.0

WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>
Cc: Anan Sun <anan.sun@mediatek.com>,
	devicetree@vger.kernel.org, Jun Yan <jun.yan@mediatek.com>,
	wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
	Chao Hao <chao.hao@mediatek.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org,
	Cui Zhang <zhang.cui@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779
Date: Sun, 5 Jan 2020 18:45:11 +0800	[thread overview]
Message-ID: <20200105104523.31006-8-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com>

When some platforms(ex:later mt6779) define has_wr_len variable,
we need to set REG_MMU_WR_LEN to improve performance. So we add
REG_MMU_WR_LEN register define in this patch.

Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 11 +++++++++++
 drivers/iommu/mtk_iommu.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5de13ab1094e..ad5690350d6a 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -44,6 +44,8 @@
 
 #define REG_MMU_MISC_CTRL			0x048
 #define REG_MMU_DCM_DIS				0x050
+#define REG_MMU_WR_LEN				0x054
+#define F_MMU_WR_THROT_DIS			(BIT(5) |  BIT(21))
 
 #define REG_MMU_CTRL_REG			0x110
 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR		(2 << 4)
@@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 	}
 	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 
+	if (data->plat_data->has_wr_len) {
+		/* write command throttling mode */
+		regval = readl_relaxed(data->base + REG_MMU_WR_LEN);
+		regval &= ~F_MMU_WR_THROT_DIS;
+		writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
+	}
+
 	if (data->plat_data->reset_axi)
 		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
 
@@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 	struct mtk_iommu_suspend_reg *reg = &data->reg;
 	void __iomem *base = data->base;
 
+	reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN);
 	reg->standard_axi_mode = readl_relaxed(base +
 					       REG_MMU_MISC_CTRL);
 	reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
@@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
 		dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
 		return ret;
 	}
+	writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN);
 	writel_relaxed(reg->standard_axi_mode,
 		       base + REG_MMU_MISC_CTRL);
 	writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index d4495230c6e7..0623f199e96f 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg {
 	u32				int_main_control;
 	u32				ivrp_paddr;
 	u32				vld_pa_rng;
+	u32				wr_len;
 };
 
 enum mtk_iommu_plat {
@@ -43,6 +44,7 @@ struct mtk_iommu_plat_data {
 	bool                has_sub_comm[2];
 	bool                has_vld_pa_rng;
 	bool                reset_axi;
+	bool                has_wr_len;
 	u32                 m4u1_mask;
 	u32                 inv_sel_reg;
 	unsigned char       larbid_remap[2][MTK_LARB_NR_MAX];
-- 
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: Anan Sun <anan.sun@mediatek.com>,
	devicetree@vger.kernel.org, Jun Yan <jun.yan@mediatek.com>,
	wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
	Chao Hao <chao.hao@mediatek.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org,
	Yong Wu <yong.wu@mediatek.com>,
	Cui Zhang <zhang.cui@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779
Date: Sun, 5 Jan 2020 18:45:11 +0800	[thread overview]
Message-ID: <20200105104523.31006-8-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com>

When some platforms(ex:later mt6779) define has_wr_len variable,
we need to set REG_MMU_WR_LEN to improve performance. So we add
REG_MMU_WR_LEN register define in this patch.

Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 11 +++++++++++
 drivers/iommu/mtk_iommu.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5de13ab1094e..ad5690350d6a 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -44,6 +44,8 @@
 
 #define REG_MMU_MISC_CTRL			0x048
 #define REG_MMU_DCM_DIS				0x050
+#define REG_MMU_WR_LEN				0x054
+#define F_MMU_WR_THROT_DIS			(BIT(5) |  BIT(21))
 
 #define REG_MMU_CTRL_REG			0x110
 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR		(2 << 4)
@@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 	}
 	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 
+	if (data->plat_data->has_wr_len) {
+		/* write command throttling mode */
+		regval = readl_relaxed(data->base + REG_MMU_WR_LEN);
+		regval &= ~F_MMU_WR_THROT_DIS;
+		writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
+	}
+
 	if (data->plat_data->reset_axi)
 		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
 
@@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 	struct mtk_iommu_suspend_reg *reg = &data->reg;
 	void __iomem *base = data->base;
 
+	reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN);
 	reg->standard_axi_mode = readl_relaxed(base +
 					       REG_MMU_MISC_CTRL);
 	reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
@@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
 		dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
 		return ret;
 	}
+	writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN);
 	writel_relaxed(reg->standard_axi_mode,
 		       base + REG_MMU_MISC_CTRL);
 	writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index d4495230c6e7..0623f199e96f 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg {
 	u32				int_main_control;
 	u32				ivrp_paddr;
 	u32				vld_pa_rng;
+	u32				wr_len;
 };
 
 enum mtk_iommu_plat {
@@ -43,6 +44,7 @@ struct mtk_iommu_plat_data {
 	bool                has_sub_comm[2];
 	bool                has_vld_pa_rng;
 	bool                reset_axi;
+	bool                has_wr_len;
 	u32                 m4u1_mask;
 	u32                 inv_sel_reg;
 	unsigned char       larbid_remap[2][MTK_LARB_NR_MAX];
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: Anan Sun <anan.sun@mediatek.com>,
	devicetree@vger.kernel.org, Jun Yan <jun.yan@mediatek.com>,
	wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
	Chao Hao <chao.hao@mediatek.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org,
	Yong Wu <yong.wu@mediatek.com>,
	Cui Zhang <zhang.cui@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779
Date: Sun, 5 Jan 2020 18:45:11 +0800	[thread overview]
Message-ID: <20200105104523.31006-8-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com>

When some platforms(ex:later mt6779) define has_wr_len variable,
we need to set REG_MMU_WR_LEN to improve performance. So we add
REG_MMU_WR_LEN register define in this patch.

Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 11 +++++++++++
 drivers/iommu/mtk_iommu.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5de13ab1094e..ad5690350d6a 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -44,6 +44,8 @@
 
 #define REG_MMU_MISC_CTRL			0x048
 #define REG_MMU_DCM_DIS				0x050
+#define REG_MMU_WR_LEN				0x054
+#define F_MMU_WR_THROT_DIS			(BIT(5) |  BIT(21))
 
 #define REG_MMU_CTRL_REG			0x110
 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR		(2 << 4)
@@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 	}
 	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 
+	if (data->plat_data->has_wr_len) {
+		/* write command throttling mode */
+		regval = readl_relaxed(data->base + REG_MMU_WR_LEN);
+		regval &= ~F_MMU_WR_THROT_DIS;
+		writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
+	}
+
 	if (data->plat_data->reset_axi)
 		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
 
@@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 	struct mtk_iommu_suspend_reg *reg = &data->reg;
 	void __iomem *base = data->base;
 
+	reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN);
 	reg->standard_axi_mode = readl_relaxed(base +
 					       REG_MMU_MISC_CTRL);
 	reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
@@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
 		dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
 		return ret;
 	}
+	writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN);
 	writel_relaxed(reg->standard_axi_mode,
 		       base + REG_MMU_MISC_CTRL);
 	writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index d4495230c6e7..0623f199e96f 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg {
 	u32				int_main_control;
 	u32				ivrp_paddr;
 	u32				vld_pa_rng;
+	u32				wr_len;
 };
 
 enum mtk_iommu_plat {
@@ -43,6 +44,7 @@ struct mtk_iommu_plat_data {
 	bool                has_sub_comm[2];
 	bool                has_vld_pa_rng;
 	bool                reset_axi;
+	bool                has_wr_len;
 	u32                 m4u1_mask;
 	u32                 inv_sel_reg;
 	unsigned char       larbid_remap[2][MTK_LARB_NR_MAX];
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2020-01-05 10:46 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-06 21:57   ` Rob Herring
2020-01-06 21:57     ` Rob Herring
2020-01-06 21:57     ` Rob Herring
2020-01-06 21:57     ` Rob Herring
2020-01-07 11:10     ` chao hao
2020-01-07 11:10       ` chao hao
2020-01-07 11:10       ` chao hao
2020-01-07 11:10       ` chao hao
2020-01-05 10:45 ` [PATCH v2 02/19] iommu/mediatek: Add m4u1_mask to distinguish m4u_id Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 03/19] iommu/mediatek: Extend larb_remap to larb_remap[2] Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 04/19] iommu/mediatek: Rename offset=0x48 register Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 05/19] iommu/mediatek: Put inv_sel_reg in the plat_data for preparing add 0x2c support in mt6779 Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 06/19] iommu/mediatek: Add new flow to get SUB_COMMON ID in translation fault Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` Chao Hao [this message]
2020-01-05 10:45   ` [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779 Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 08/19] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 09/19] iommu/mediatek: Add mtk_iommu_pgtable structure Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 10/19] iommu/mediatek: Remove mtk_iommu_domain_finalise Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 11/19] iommu/mediatek: Remove pgtable info in mtk_iommu_domain Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 12/19] iommu/mediatek: Change get the way of m4u_group Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 13/19] iommu/mediatek: Add smi_larb info about device Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 15/19] iommu/mediatek: Remove the usage of m4u_dom variable Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 16/19] iommu/mediatek: Remove mtk_iommu_get_m4u_data api Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 17/19] iommu/mediatek: Add iova reserved function Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 18/19] iommu/mediatek: Change single domain to multiple domains Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779 Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao
2020-01-05 10:45   ` Chao Hao

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