From: Julien Thierry <jthierry@redhat.com> To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: jpoimboe@redhat.com, peterz@infradead.org, raphael.gault@arm.com, catalin.marinas@arm.com, will@kernel.org, Julien Thierry <jthierry@redhat.com> Subject: [RFC v5 40/57] objtool: arm64: Decode register data processing instructions Date: Thu, 9 Jan 2020 16:02:43 +0000 [thread overview] Message-ID: <20200109160300.26150-41-jthierry@redhat.com> (raw) In-Reply-To: <20200109160300.26150-1-jthierry@redhat.com> Decode data processing instructions with more than one register as input operand. Due to these multiple register inputs, objtool cannot rely on those instructions to track the CFA state. Luckily, the compiler does not tend to generate these instructions to modify the stack or frame pointer. Suggested-by: Raphael Gault <raphael.gault@arm.com> Signed-off-by: Julien Thierry <jthierry@redhat.com> --- tools/objtool/arch/arm64/decode.c | 471 ++++++++++++++++++ .../objtool/arch/arm64/include/insn_decode.h | 42 ++ 2 files changed, 513 insertions(+) diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index aed8ba0f812e..bb1ba3b0997f 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -128,10 +128,12 @@ static arm_decode_class aarch64_insn_class_decode_table[NR_INSN_CLASS] = { [INSN_UNKNOWN] = arm_decode_unknown, [INSN_UNALLOC] = arm_decode_unknown, [INSN_LD_ST_4] = arm_decode_ld_st, + [INSN_DP_REG_5] = arm_decode_dp_reg, [INSN_LD_ST_6] = arm_decode_ld_st, [0b1000 ... INSN_DP_IMM] = arm_decode_dp_imm, [0b1010 ... INSN_SYS_BRANCH] = arm_decode_br_sys, [INSN_LD_ST_C] = arm_decode_ld_st, + [INSN_DP_REG_D] = arm_decode_dp_reg, [INSN_LD_ST_E] = arm_decode_ld_st, }; @@ -2275,3 +2277,472 @@ int arm_decode_ld_st_mem_tags(u32 instr, enum insn_type *type, return -1; } + +static struct aarch64_insn_decoder dp_reg_decoder[] = { + { + .mask = 0b111111000000, + .value = 0b010110000000, + .decode_func = arm_decode_dp_reg_2src, + }, + { + .mask = 0b111111000000, + .value = 0b110110000000, + .decode_func = arm_decode_dp_reg_1src, + }, + { + .mask = 0b011000000000, + .value = 0b000000000000, + .decode_func = arm_decode_dp_reg_logi, + }, + { + .mask = 0b011001000000, + .value = 0b001000000000, + .decode_func = arm_decode_dp_reg_adds, + }, + { + .mask = 0b011001000000, + .value = 0b001001000000, + .decode_func = arm_decode_dp_reg_adde, + }, + { + .mask = 0b011111111111, + .value = 0b010000000000, + .decode_func = arm_decode_dp_reg_addc, + }, + { + .mask = 0b011111011111, + .value = 0b010000000001, + .decode_func = arm_decode_dp_reg_rota, + }, + { + .mask = 0b011111001111, + .value = 0b010000000010, + .decode_func = arm_decode_dp_reg_eval, + }, + { + .mask = 0b011111000010, + .value = 0b010010000000, + .decode_func = arm_decode_dp_reg_cmpr, + }, + { + .mask = 0b011111000010, + .value = 0b010010000010, + .decode_func = arm_decode_dp_reg_cmpi, + }, + { + .mask = 0b011111000000, + .value = 0b010100000000, + .decode_func = arm_decode_dp_reg_csel, + }, + { + .mask = 0b011000000000, + .value = 0b011000000000, + .decode_func = arm_decode_dp_reg_3src, + }, +}; + +int arm_decode_dp_reg(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char op0 = 0, op1 = 0, op2 = 0, op3 = 0; + u32 decode_field = 0; + int i = 0; + + op0 = EXTRACT_BIT(instr, 30); + op1 = EXTRACT_BIT(instr, 28); + op2 = (instr >> 21) & ONES(4); + op3 = (instr >> 10) & ONES(6); + decode_field = (op0 << 5) | (op1 << 4) | op2; + decode_field = (decode_field << 6) | op3; + + for (i = 0; i < ARRAY_SIZE(dp_reg_decoder); i++) { + if ((decode_field & dp_reg_decoder[i].mask) == + dp_reg_decoder[i].value) { + return dp_reg_decoder[i].decode_func(instr, type, + immediate, ops_list); + } + } + return arm_decode_unknown(instr, type, immediate, ops_list); +} + +static struct aarch64_insn_decoder dp_reg_2src_decoder[] = { + { + .mask = 0b00111111, + .value = 0b00000001, + }, + { + .mask = 0b00111000, + .value = 0b00011000, + }, + { + .mask = 0b00100000, + .value = 0b00100000, + }, + { + .mask = 0b01111111, + .value = 0b00000101, + }, + { + .mask = 0b01111100, + .value = 0b00001100, + }, + { + .mask = 0b01111110, + .value = 0b01000010, + }, + { + .mask = 0b01111100, + .value = 0b01000100, + }, + { + .mask = 0b01111000, + .value = 0b01001000, + }, + { + .mask = 0b01110000, + .value = 0b01010000, + }, + { + .mask = 0b10111111, + .value = 0b00000000, + }, + { + .mask = 0b11111111, + .value = 0b00000100, + }, + { + .mask = 0b11111110, + .value = 0b00000110, + }, + { + .mask = 0b11111011, + .value = 0b00010011, + }, + { + .mask = 0b11111001, + .value = 0b10010000, + }, + { + .mask = 0b11111010, + .value = 0b10010000, + }, +}; + +int arm_decode_dp_reg_2src(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, opcode = 0; + unsigned char decode_field = 0; + int i = 0; + + sf = EXTRACT_BIT(instr, 31); + S = EXTRACT_BIT(instr, 29); + opcode = (instr >> 10) & ONES(6); + + decode_field = (sf << 7) | (S << 6) | opcode; + + for (i = 0; i < ARRAY_SIZE(dp_reg_2src_decoder); i++) { + if ((decode_field & dp_reg_2src_decoder[i].mask) == + dp_reg_2src_decoder[i].value) { + return arm_decode_unknown(instr, type, immediate, + ops_list); + } + } + + *type = INSN_OTHER; + return 0; +} + +static struct aarch64_insn_decoder dp_reg_1src_decoder[] = { + { + .mask = 0b0000000001000, + .value = 0b0000000001000, + }, + { + .mask = 0b0000000010000, + .value = 0b0000000010000, + }, + { + .mask = 0b0000000100000, + .value = 0b0000000100000, + }, + { + .mask = 0b0000001000000, + .value = 0b0000001000000, + }, + { + .mask = 0b0000010000000, + .value = 0b0000010000000, + }, + { + .mask = 0b0000100000000, + .value = 0b0000100000000, + }, + { + .mask = 0b0001000000000, + .value = 0b0001000000000, + }, + { + .mask = 0b0010000000000, + .value = 0b0010000000000, + }, + { + .mask = 0b0111111111110, + .value = 0b0000000000110, + }, + { + .mask = 0b0100000000000, + .value = 0b0100000000000, + }, +}; + +int arm_decode_dp_reg_1src(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, opcode2 = 0, opcode = 0; + u32 decode_field = 0; + int i = 0; + + sf = EXTRACT_BIT(instr, 31); + S = EXTRACT_BIT(instr, 29); + opcode2 = (instr >> 16) & ONES(5); + opcode = (instr >> 10) & ONES(6); + + decode_field = (sf << 6) | (S << 5) | opcode2; + decode_field = (decode_field << 6) | opcode; + + for (i = 0; i < ARRAY_SIZE(dp_reg_1src_decoder); i++) { + if ((decode_field & dp_reg_1src_decoder[i].mask) == + dp_reg_1src_decoder[i].value) { + return arm_decode_unknown(instr, type, immediate, + ops_list); + } + } + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_logi(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, imm6 = 0; + + sf = EXTRACT_BIT(instr, 31); + imm6 = (instr >> 10) & ONES(6); + + if (imm6 >= 0b100000 && !sf) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_adds(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, shift = 0, imm6 = 0; + + sf = EXTRACT_BIT(instr, 31); + shift = (instr >> 22) & ONES(2); + imm6 = (instr >> 10) & ONES(6); + + if ((imm6 >= 0b100000 && !sf) || shift == 0b11) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_adde(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char opt = 0, imm3 = 0; + + opt = (instr >> 22) & ONES(2); + imm3 = (instr >> 10) & ONES(3); + + if (opt != 0 || imm3 >= 0b101) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_addc(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_rota(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, op_bit = 0, o2 = 0; + unsigned char decode_field = 0; + + sf = EXTRACT_BIT(instr, 31); + op_bit = EXTRACT_BIT(instr, 30); + S = EXTRACT_BIT(instr, 29); + o2 = EXTRACT_BIT(instr, 4); + + decode_field = (sf << 3) | (op_bit << 2) | (S << 1) | o2; + + if (decode_field != 0b1010) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_eval(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, op_bit = 0, o3 = 0, sz = 0; + unsigned char opcode2 = 0, mask = 0; + u32 decode_field = 0; + + sf = EXTRACT_BIT(instr, 31); + op_bit = EXTRACT_BIT(instr, 30); + S = EXTRACT_BIT(instr, 29); + sz = EXTRACT_BIT(instr, 14); + o3 = EXTRACT_BIT(instr, 4); + + opcode2 = (instr >> 15) & ONES(6); + mask = instr & ONES(4); + + decode_field = (sf << 2) | (op_bit << 1) | S; + decode_field = (decode_field << 12) | (opcode2 << 6) | (sz << 5); + decode_field |= (o3 << 4) | mask; + +#define DP_EVAL_SETF_1 0b001000000001101 +#define DP_EVAL_SETF_2 0b001000000101101 + + if (decode_field != DP_EVAL_SETF_1 && + decode_field != DP_EVAL_SETF_2) { + return arm_decode_unknown(instr, type, immediate, ops_list); + } + + *type = INSN_OTHER; + return 0; +#undef DP_EVAL_SETF_1 +#undef DP_EVAL_SETF_2 +} + +int arm_decode_dp_reg_cmpr(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char S = 0, o2 = 0, o3 = 0; + + S = EXTRACT_BIT(instr, 29); + o2 = EXTRACT_BIT(instr, 10); + o3 = EXTRACT_BIT(instr, 4); + + if (!S || o2 || o3) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_csel(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char S = 0, op2 = 0; + + S = EXTRACT_BIT(instr, 29); + op2 = (instr >> 10) & ONES(2); + + if (S || op2 >= 0b10) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_cmpi(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + return arm_decode_dp_reg_cmpr(instr, type, immediate, ops_list); +} + +static struct aarch64_insn_decoder dp_reg_3src_decoder[] = { + { + .mask = 0b0111111, + .value = 0b0000101, + }, + { + .mask = 0b0111110, + .value = 0b0000110, + }, + { + .mask = 0b0111110, + .value = 0b0001000, + }, + { + .mask = 0b0111111, + .value = 0b0001101, + }, + { + .mask = 0b0111110, + .value = 0b0001110, + }, + { + .mask = 0b0110000, + .value = 0b0010000, + }, + { + .mask = 0b0100000, + .value = 0b0100000, + }, + { + .mask = 0b1111111, + .value = 0b0000010, + }, + { + .mask = 0b1111111, + .value = 0b0000011, + }, + { + .mask = 0b1111111, + .value = 0b0000100, + }, + { + .mask = 0b1111111, + .value = 0b0001010, + }, + { + .mask = 0b1111111, + .value = 0b0001011, + }, + { + .mask = 0b1111111, + .value = 0b0001100, + }, +}; + +int arm_decode_dp_reg_3src(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, op54 = 0, op31 = 0, o0 = 0; + unsigned char decode_field = 0; + int i = 0; + + sf = EXTRACT_BIT(instr, 31); + op54 = (instr >> 29) & ONES(2); + op31 = (instr >> 21) & ONES(3); + o0 = EXTRACT_BIT(instr, 15); + + decode_field = (sf << 6) | (op54 << 4) | (op31 << 1) | o0; + + for (i = 0; i < ARRAY_SIZE(dp_reg_3src_decoder); i++) { + if ((decode_field & dp_reg_3src_decoder[i].mask) == + dp_reg_3src_decoder[i].value) { + return arm_decode_unknown(instr, type, immediate, + ops_list); + } + } + + *type = INSN_OTHER; + return 0; +} diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h index 3ec4c69547ac..8fb2f2b7564f 100644 --- a/tools/objtool/arch/arm64/include/insn_decode.h +++ b/tools/objtool/arch/arm64/include/insn_decode.h @@ -14,6 +14,8 @@ #define INSN_LD_ST_6 0b0110 //0bx1x0 #define INSN_LD_ST_C 0b1100 //0bx1x0 #define INSN_LD_ST_E 0b1110 //0bx1x0 +#define INSN_DP_REG_5 0b0101 //0bx101 +#define INSN_DP_REG_D 0b1101 //0bx101 #define NR_INSN_CLASS 16 #define INSN_CLASS(opcode) (((opcode) >> 25) & (NR_INSN_CLASS - 1)) @@ -39,6 +41,8 @@ struct aarch64_insn_decoder { /* arm64 instruction classes */ int arm_decode_dp_imm(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); +int arm_decode_dp_reg(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list); int arm_decode_br_sys(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); int arm_decode_ld_st(u32 instr, enum insn_type *type, @@ -153,4 +157,42 @@ int arm_decode_ld_st_regs_unsigned(u32 instr, enum insn_type *type, int arm_decode_ld_st_exclusive(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); + +/* arm64 data processing -- registers instructions */ +int arm_decode_dp_reg_1src(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_2src(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_3src(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_adde(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_cmpi(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_eval(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_cmpr(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_rota(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_csel(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_addc(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_adds(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_logi(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); #endif /* _ARM_INSN_DECODE_H */ -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Julien Thierry <jthierry@redhat.com> To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Julien Thierry <jthierry@redhat.com>, peterz@infradead.org, catalin.marinas@arm.com, raphael.gault@arm.com, jpoimboe@redhat.com, will@kernel.org Subject: [RFC v5 40/57] objtool: arm64: Decode register data processing instructions Date: Thu, 9 Jan 2020 16:02:43 +0000 [thread overview] Message-ID: <20200109160300.26150-41-jthierry@redhat.com> (raw) In-Reply-To: <20200109160300.26150-1-jthierry@redhat.com> Decode data processing instructions with more than one register as input operand. Due to these multiple register inputs, objtool cannot rely on those instructions to track the CFA state. Luckily, the compiler does not tend to generate these instructions to modify the stack or frame pointer. Suggested-by: Raphael Gault <raphael.gault@arm.com> Signed-off-by: Julien Thierry <jthierry@redhat.com> --- tools/objtool/arch/arm64/decode.c | 471 ++++++++++++++++++ .../objtool/arch/arm64/include/insn_decode.h | 42 ++ 2 files changed, 513 insertions(+) diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index aed8ba0f812e..bb1ba3b0997f 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -128,10 +128,12 @@ static arm_decode_class aarch64_insn_class_decode_table[NR_INSN_CLASS] = { [INSN_UNKNOWN] = arm_decode_unknown, [INSN_UNALLOC] = arm_decode_unknown, [INSN_LD_ST_4] = arm_decode_ld_st, + [INSN_DP_REG_5] = arm_decode_dp_reg, [INSN_LD_ST_6] = arm_decode_ld_st, [0b1000 ... INSN_DP_IMM] = arm_decode_dp_imm, [0b1010 ... INSN_SYS_BRANCH] = arm_decode_br_sys, [INSN_LD_ST_C] = arm_decode_ld_st, + [INSN_DP_REG_D] = arm_decode_dp_reg, [INSN_LD_ST_E] = arm_decode_ld_st, }; @@ -2275,3 +2277,472 @@ int arm_decode_ld_st_mem_tags(u32 instr, enum insn_type *type, return -1; } + +static struct aarch64_insn_decoder dp_reg_decoder[] = { + { + .mask = 0b111111000000, + .value = 0b010110000000, + .decode_func = arm_decode_dp_reg_2src, + }, + { + .mask = 0b111111000000, + .value = 0b110110000000, + .decode_func = arm_decode_dp_reg_1src, + }, + { + .mask = 0b011000000000, + .value = 0b000000000000, + .decode_func = arm_decode_dp_reg_logi, + }, + { + .mask = 0b011001000000, + .value = 0b001000000000, + .decode_func = arm_decode_dp_reg_adds, + }, + { + .mask = 0b011001000000, + .value = 0b001001000000, + .decode_func = arm_decode_dp_reg_adde, + }, + { + .mask = 0b011111111111, + .value = 0b010000000000, + .decode_func = arm_decode_dp_reg_addc, + }, + { + .mask = 0b011111011111, + .value = 0b010000000001, + .decode_func = arm_decode_dp_reg_rota, + }, + { + .mask = 0b011111001111, + .value = 0b010000000010, + .decode_func = arm_decode_dp_reg_eval, + }, + { + .mask = 0b011111000010, + .value = 0b010010000000, + .decode_func = arm_decode_dp_reg_cmpr, + }, + { + .mask = 0b011111000010, + .value = 0b010010000010, + .decode_func = arm_decode_dp_reg_cmpi, + }, + { + .mask = 0b011111000000, + .value = 0b010100000000, + .decode_func = arm_decode_dp_reg_csel, + }, + { + .mask = 0b011000000000, + .value = 0b011000000000, + .decode_func = arm_decode_dp_reg_3src, + }, +}; + +int arm_decode_dp_reg(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char op0 = 0, op1 = 0, op2 = 0, op3 = 0; + u32 decode_field = 0; + int i = 0; + + op0 = EXTRACT_BIT(instr, 30); + op1 = EXTRACT_BIT(instr, 28); + op2 = (instr >> 21) & ONES(4); + op3 = (instr >> 10) & ONES(6); + decode_field = (op0 << 5) | (op1 << 4) | op2; + decode_field = (decode_field << 6) | op3; + + for (i = 0; i < ARRAY_SIZE(dp_reg_decoder); i++) { + if ((decode_field & dp_reg_decoder[i].mask) == + dp_reg_decoder[i].value) { + return dp_reg_decoder[i].decode_func(instr, type, + immediate, ops_list); + } + } + return arm_decode_unknown(instr, type, immediate, ops_list); +} + +static struct aarch64_insn_decoder dp_reg_2src_decoder[] = { + { + .mask = 0b00111111, + .value = 0b00000001, + }, + { + .mask = 0b00111000, + .value = 0b00011000, + }, + { + .mask = 0b00100000, + .value = 0b00100000, + }, + { + .mask = 0b01111111, + .value = 0b00000101, + }, + { + .mask = 0b01111100, + .value = 0b00001100, + }, + { + .mask = 0b01111110, + .value = 0b01000010, + }, + { + .mask = 0b01111100, + .value = 0b01000100, + }, + { + .mask = 0b01111000, + .value = 0b01001000, + }, + { + .mask = 0b01110000, + .value = 0b01010000, + }, + { + .mask = 0b10111111, + .value = 0b00000000, + }, + { + .mask = 0b11111111, + .value = 0b00000100, + }, + { + .mask = 0b11111110, + .value = 0b00000110, + }, + { + .mask = 0b11111011, + .value = 0b00010011, + }, + { + .mask = 0b11111001, + .value = 0b10010000, + }, + { + .mask = 0b11111010, + .value = 0b10010000, + }, +}; + +int arm_decode_dp_reg_2src(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, opcode = 0; + unsigned char decode_field = 0; + int i = 0; + + sf = EXTRACT_BIT(instr, 31); + S = EXTRACT_BIT(instr, 29); + opcode = (instr >> 10) & ONES(6); + + decode_field = (sf << 7) | (S << 6) | opcode; + + for (i = 0; i < ARRAY_SIZE(dp_reg_2src_decoder); i++) { + if ((decode_field & dp_reg_2src_decoder[i].mask) == + dp_reg_2src_decoder[i].value) { + return arm_decode_unknown(instr, type, immediate, + ops_list); + } + } + + *type = INSN_OTHER; + return 0; +} + +static struct aarch64_insn_decoder dp_reg_1src_decoder[] = { + { + .mask = 0b0000000001000, + .value = 0b0000000001000, + }, + { + .mask = 0b0000000010000, + .value = 0b0000000010000, + }, + { + .mask = 0b0000000100000, + .value = 0b0000000100000, + }, + { + .mask = 0b0000001000000, + .value = 0b0000001000000, + }, + { + .mask = 0b0000010000000, + .value = 0b0000010000000, + }, + { + .mask = 0b0000100000000, + .value = 0b0000100000000, + }, + { + .mask = 0b0001000000000, + .value = 0b0001000000000, + }, + { + .mask = 0b0010000000000, + .value = 0b0010000000000, + }, + { + .mask = 0b0111111111110, + .value = 0b0000000000110, + }, + { + .mask = 0b0100000000000, + .value = 0b0100000000000, + }, +}; + +int arm_decode_dp_reg_1src(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, opcode2 = 0, opcode = 0; + u32 decode_field = 0; + int i = 0; + + sf = EXTRACT_BIT(instr, 31); + S = EXTRACT_BIT(instr, 29); + opcode2 = (instr >> 16) & ONES(5); + opcode = (instr >> 10) & ONES(6); + + decode_field = (sf << 6) | (S << 5) | opcode2; + decode_field = (decode_field << 6) | opcode; + + for (i = 0; i < ARRAY_SIZE(dp_reg_1src_decoder); i++) { + if ((decode_field & dp_reg_1src_decoder[i].mask) == + dp_reg_1src_decoder[i].value) { + return arm_decode_unknown(instr, type, immediate, + ops_list); + } + } + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_logi(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, imm6 = 0; + + sf = EXTRACT_BIT(instr, 31); + imm6 = (instr >> 10) & ONES(6); + + if (imm6 >= 0b100000 && !sf) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_adds(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, shift = 0, imm6 = 0; + + sf = EXTRACT_BIT(instr, 31); + shift = (instr >> 22) & ONES(2); + imm6 = (instr >> 10) & ONES(6); + + if ((imm6 >= 0b100000 && !sf) || shift == 0b11) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_adde(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char opt = 0, imm3 = 0; + + opt = (instr >> 22) & ONES(2); + imm3 = (instr >> 10) & ONES(3); + + if (opt != 0 || imm3 >= 0b101) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_addc(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_rota(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, op_bit = 0, o2 = 0; + unsigned char decode_field = 0; + + sf = EXTRACT_BIT(instr, 31); + op_bit = EXTRACT_BIT(instr, 30); + S = EXTRACT_BIT(instr, 29); + o2 = EXTRACT_BIT(instr, 4); + + decode_field = (sf << 3) | (op_bit << 2) | (S << 1) | o2; + + if (decode_field != 0b1010) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_eval(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, S = 0, op_bit = 0, o3 = 0, sz = 0; + unsigned char opcode2 = 0, mask = 0; + u32 decode_field = 0; + + sf = EXTRACT_BIT(instr, 31); + op_bit = EXTRACT_BIT(instr, 30); + S = EXTRACT_BIT(instr, 29); + sz = EXTRACT_BIT(instr, 14); + o3 = EXTRACT_BIT(instr, 4); + + opcode2 = (instr >> 15) & ONES(6); + mask = instr & ONES(4); + + decode_field = (sf << 2) | (op_bit << 1) | S; + decode_field = (decode_field << 12) | (opcode2 << 6) | (sz << 5); + decode_field |= (o3 << 4) | mask; + +#define DP_EVAL_SETF_1 0b001000000001101 +#define DP_EVAL_SETF_2 0b001000000101101 + + if (decode_field != DP_EVAL_SETF_1 && + decode_field != DP_EVAL_SETF_2) { + return arm_decode_unknown(instr, type, immediate, ops_list); + } + + *type = INSN_OTHER; + return 0; +#undef DP_EVAL_SETF_1 +#undef DP_EVAL_SETF_2 +} + +int arm_decode_dp_reg_cmpr(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char S = 0, o2 = 0, o3 = 0; + + S = EXTRACT_BIT(instr, 29); + o2 = EXTRACT_BIT(instr, 10); + o3 = EXTRACT_BIT(instr, 4); + + if (!S || o2 || o3) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_csel(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char S = 0, op2 = 0; + + S = EXTRACT_BIT(instr, 29); + op2 = (instr >> 10) & ONES(2); + + if (S || op2 >= 0b10) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + return 0; +} + +int arm_decode_dp_reg_cmpi(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + return arm_decode_dp_reg_cmpr(instr, type, immediate, ops_list); +} + +static struct aarch64_insn_decoder dp_reg_3src_decoder[] = { + { + .mask = 0b0111111, + .value = 0b0000101, + }, + { + .mask = 0b0111110, + .value = 0b0000110, + }, + { + .mask = 0b0111110, + .value = 0b0001000, + }, + { + .mask = 0b0111111, + .value = 0b0001101, + }, + { + .mask = 0b0111110, + .value = 0b0001110, + }, + { + .mask = 0b0110000, + .value = 0b0010000, + }, + { + .mask = 0b0100000, + .value = 0b0100000, + }, + { + .mask = 0b1111111, + .value = 0b0000010, + }, + { + .mask = 0b1111111, + .value = 0b0000011, + }, + { + .mask = 0b1111111, + .value = 0b0000100, + }, + { + .mask = 0b1111111, + .value = 0b0001010, + }, + { + .mask = 0b1111111, + .value = 0b0001011, + }, + { + .mask = 0b1111111, + .value = 0b0001100, + }, +}; + +int arm_decode_dp_reg_3src(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, op54 = 0, op31 = 0, o0 = 0; + unsigned char decode_field = 0; + int i = 0; + + sf = EXTRACT_BIT(instr, 31); + op54 = (instr >> 29) & ONES(2); + op31 = (instr >> 21) & ONES(3); + o0 = EXTRACT_BIT(instr, 15); + + decode_field = (sf << 6) | (op54 << 4) | (op31 << 1) | o0; + + for (i = 0; i < ARRAY_SIZE(dp_reg_3src_decoder); i++) { + if ((decode_field & dp_reg_3src_decoder[i].mask) == + dp_reg_3src_decoder[i].value) { + return arm_decode_unknown(instr, type, immediate, + ops_list); + } + } + + *type = INSN_OTHER; + return 0; +} diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h index 3ec4c69547ac..8fb2f2b7564f 100644 --- a/tools/objtool/arch/arm64/include/insn_decode.h +++ b/tools/objtool/arch/arm64/include/insn_decode.h @@ -14,6 +14,8 @@ #define INSN_LD_ST_6 0b0110 //0bx1x0 #define INSN_LD_ST_C 0b1100 //0bx1x0 #define INSN_LD_ST_E 0b1110 //0bx1x0 +#define INSN_DP_REG_5 0b0101 //0bx101 +#define INSN_DP_REG_D 0b1101 //0bx101 #define NR_INSN_CLASS 16 #define INSN_CLASS(opcode) (((opcode) >> 25) & (NR_INSN_CLASS - 1)) @@ -39,6 +41,8 @@ struct aarch64_insn_decoder { /* arm64 instruction classes */ int arm_decode_dp_imm(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); +int arm_decode_dp_reg(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list); int arm_decode_br_sys(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); int arm_decode_ld_st(u32 instr, enum insn_type *type, @@ -153,4 +157,42 @@ int arm_decode_ld_st_regs_unsigned(u32 instr, enum insn_type *type, int arm_decode_ld_st_exclusive(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); + +/* arm64 data processing -- registers instructions */ +int arm_decode_dp_reg_1src(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_2src(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_3src(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_adde(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_cmpi(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_eval(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_cmpr(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_rota(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_csel(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_addc(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_adds(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); +int arm_decode_dp_reg_logi(u32 instr, enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list); #endif /* _ARM_INSN_DECODE_H */ -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-01-09 16:08 UTC|newest] Thread overview: 189+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-09 16:02 [RFC v5 00/57] objtool: Add support for arm64 Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 01/57] objtool: check: Remove redundant checks on operand type Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 02/57] objtool: check: Clean instruction state before each function validation Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 03/57] objtool: check: Use arch specific values in restore_reg() Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 04/57] objtool: check: Ignore empty alternative groups Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-21 16:30 ` Josh Poimboeuf 2020-01-21 16:30 ` Josh Poimboeuf 2020-01-23 11:45 ` Julien Thierry 2020-01-23 11:45 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 05/57] objtool: Add abstraction for computation of symbols offsets Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 06/57] objtool: Give ORC functions consistent name Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 07/57] objtool: orc: Refactor ORC API for other architectures to implement Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 08/57] objtool: Make ORC support optional Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-21 16:37 ` Josh Poimboeuf 2020-01-21 16:37 ` Josh Poimboeuf 2020-01-23 11:45 ` Julien Thierry 2020-01-23 11:45 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 09/57] objtool: Move registers and control flow to arch-dependent code Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 10/57] objtool: Split generic and arch specific CFI definitions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 11/57] objtool: Abstract alternative special case handling Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-20 14:54 ` Peter Zijlstra 2020-01-20 14:54 ` Peter Zijlstra 2020-01-23 11:45 ` Julien Thierry 2020-01-23 11:45 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 12/57] objtool: check: Allow jumps from an alternative group to itself Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-20 14:56 ` Peter Zijlstra 2020-01-20 14:56 ` Peter Zijlstra 2020-01-21 10:30 ` Will Deacon 2020-01-21 10:30 ` Will Deacon 2020-01-21 17:33 ` Josh Poimboeuf 2020-01-21 17:33 ` Josh Poimboeuf 2020-01-23 13:42 ` Julien Thierry 2020-01-23 13:42 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 13/57] objtool: Refactor switch-tables code to support other architectures Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 14/57] objtool: Do not look for STT_NOTYPE symbols Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-11 18:49 ` kbuild test robot 2020-01-13 10:20 ` Julien Thierry 2020-01-13 10:20 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 15/57] objtool: Support addition to set frame pointer Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 16/57] objtool: Support restoring BP from the stack without POP Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 17/57] objtool: Make stack validation more generic Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 18/57] objtool: Support multiple stack_op per instruction Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 19/57] objtool: arm64: Add required implementation for supporting the aarch64 architecture in objtool Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 20/57] objtool: arm64: Decode unknown instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 21/57] objtool: arm64: Decode simple data processing instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 22/57] objtool: arm64: Decode add/sub immediate instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 23/57] objtool: arm64: Decode logical data processing instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 24/57] objtool: arm64: Decode system instructions not affecting the flow Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 25/57] objtool: arm64: Decode calls to higher EL Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 26/57] objtool: arm64: Decode brk instruction Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 27/57] objtool: arm64: Decode instruction triggering context switch Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 28/57] objtool: arm64: Decode branch instructions with PC relative immediates Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 29/57] objtool: arm64: Decode branch to register instruction Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 30/57] objtool: arm64: Decode basic load/stores Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 31/57] objtool: arm64: Decode load/store with register offset Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 32/57] objtool: arm64: Decode load/store register pair instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 33/57] objtool: arm64: Decode FP/SIMD load/store instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 34/57] objtool: arm64: Decode load/store exclusive Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 35/57] objtool: arm64: Decode atomic load/store Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 36/57] objtool: arm64: Decode pointer auth load instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 37/57] objtool: arm64: Decode load acquire/store release Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 38/57] objtool: arm64: Decode load/store with memory tag Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 39/57] objtool: arm64: Decode load literal Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` Julien Thierry [this message] 2020-01-09 16:02 ` [RFC v5 40/57] objtool: arm64: Decode register data processing instructions Julien Thierry 2020-01-09 16:02 ` [RFC v5 41/57] objtool: arm64: Decode FP/SIMD " Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 42/57] objtool: arm64: Decode SVE instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 43/57] gcc-plugins: objtool: Add plugin to detect switch table on arm64 Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 44/57] objtool: arm64: Implement functions to add switch tables alternatives Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-15 16:37 ` Raphael Gault 2020-01-15 16:37 ` Raphael Gault 2020-01-17 8:28 ` Julien Thierry 2020-01-17 8:28 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 45/57] objtool: arm64: Enable stack validation for arm64 Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-11 14:42 ` kbuild test robot 2020-01-11 20:30 ` kbuild test robot 2020-01-09 16:02 ` [RFC v5 46/57] arm64: alternative: Mark .altinstr_replacement as containing executable instructions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-12 11:08 ` kbuild test robot 2020-01-13 3:38 ` kbuild test robot 2020-01-09 16:02 ` [RFC v5 47/57] arm64: assembler: Add macro to annotate asm function having non standard stack-frame Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-21 10:30 ` Will Deacon 2020-01-21 10:30 ` Will Deacon 2020-01-23 13:45 ` Julien Thierry 2020-01-23 13:45 ` Julien Thierry 2020-01-23 14:40 ` Will Deacon 2020-01-23 14:40 ` Will Deacon 2020-01-09 16:02 ` [RFC v5 48/57] arm64: sleep: Prevent stack frame warnings from objtool Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 49/57] arm64: kvm: Annotate non-standard stack frame functions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 50/57] arm64: kernel: Add exception on kuser32 to prevent stack analysis Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 51/57] arm64: crypto: Add exceptions for crypto object " Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 52/57] arm64: kernel: Annotate non-standard stack frame functions Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 53/57] arm64: Generate no-ops to pad executable section Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 54/57] arm64: Move constant to rodata Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 55/57] arm64: Mark sigreturn32.o as containing non standard code Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:02 ` [RFC v5 56/57] arm64: entry: Avoid empty alternatives entries Julien Thierry 2020-01-09 16:02 ` Julien Thierry 2020-01-09 16:51 ` Mark Rutland 2020-01-09 16:51 ` Mark Rutland 2020-01-21 10:30 ` Will Deacon 2020-01-21 10:30 ` Will Deacon 2020-01-09 16:03 ` [RFC v5 57/57] arm64: crypto: Remove redundant branch Julien Thierry 2020-01-09 16:03 ` Julien Thierry 2020-01-12 8:42 ` [RFC v5 00/57] objtool: Add support for arm64 Nathan Chancellor 2020-01-12 8:42 ` Nathan Chancellor 2020-01-13 7:57 ` Julien Thierry 2020-01-13 7:57 ` Julien Thierry 2020-01-21 10:31 ` Will Deacon 2020-01-21 10:31 ` Will Deacon 2020-01-21 17:08 ` Nick Desaulniers 2020-01-21 17:08 ` Nick Desaulniers 2020-01-21 18:06 ` Will Deacon 2020-01-21 18:06 ` Will Deacon 2020-01-21 18:30 ` Josh Poimboeuf 2020-01-21 18:30 ` Josh Poimboeuf 2020-01-22 14:47 ` Will Deacon 2020-01-22 14:47 ` Will Deacon 2020-01-13 17:18 ` Nick Desaulniers 2020-01-13 17:18 ` Nick Desaulniers 2020-01-20 15:07 ` Peter Zijlstra 2020-01-20 15:07 ` Peter Zijlstra 2020-01-21 17:50 ` Josh Poimboeuf 2020-01-21 17:50 ` Josh Poimboeuf 2020-01-23 13:56 ` Julien Thierry 2020-01-23 13:56 ` Julien Thierry 2020-01-21 10:30 ` Will Deacon 2020-01-21 10:30 ` Will Deacon 2020-01-23 13:52 ` Julien Thierry 2020-01-23 13:52 ` Julien Thierry 2020-01-23 14:35 ` Will Deacon 2020-01-23 14:35 ` Will Deacon 2020-01-23 15:11 ` Julien Thierry 2020-01-23 15:11 ` Julien Thierry
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200109160300.26150-41-jthierry@redhat.com \ --to=jthierry@redhat.com \ --cc=catalin.marinas@arm.com \ --cc=jpoimboe@redhat.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=peterz@infradead.org \ --cc=raphael.gault@arm.com \ --cc=will@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.