From: Eric Auger <eric.auger@redhat.com> To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: andrew.murray@arm.com Subject: [PATCH 1/4] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset Date: Fri, 24 Jan 2020 15:25:32 +0100 [thread overview] Message-ID: <20200124142535.29386-2-eric.auger@redhat.com> (raw) In-Reply-To: <20200124142535.29386-1-eric.auger@redhat.com> The specification says PMSWINC increments PMEVCNTR<n>_EL1 by 1 if PMEVCNTR<n>_EL0 is enabled and configured to count SW_INCR. For PMEVCNTR<n>_EL0 to be enabled, we need both PMCNTENSET to be set for the corresponding event counter but we also need the PMCR.E bit to be set. Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC register") Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> --- virt/kvm/arm/pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 8731dfeced8b..c3f8b059881e 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -486,6 +486,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) if (val == 0) return; + if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) + return; + enable = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) { if (!(val & BIT(i))) -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Eric Auger <eric.auger@redhat.com> To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: andrew.murray@arm.com Subject: [PATCH 1/4] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset Date: Fri, 24 Jan 2020 15:25:32 +0100 [thread overview] Message-ID: <20200124142535.29386-2-eric.auger@redhat.com> (raw) In-Reply-To: <20200124142535.29386-1-eric.auger@redhat.com> The specification says PMSWINC increments PMEVCNTR<n>_EL1 by 1 if PMEVCNTR<n>_EL0 is enabled and configured to count SW_INCR. For PMEVCNTR<n>_EL0 to be enabled, we need both PMCNTENSET to be set for the corresponding event counter but we also need the PMCR.E bit to be set. Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC register") Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> --- virt/kvm/arm/pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 8731dfeced8b..c3f8b059881e 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -486,6 +486,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) if (val == 0) return; + if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) + return; + enable = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) { if (!(val & BIT(i))) -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-01-24 14:26 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-24 14:25 [PATCH 0/4] KVM/ARM: Misc PMU fixes Eric Auger 2020-01-24 14:25 ` Eric Auger 2020-01-24 14:25 ` Eric Auger [this message] 2020-01-24 14:25 ` [PATCH 1/4] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset Eric Auger 2020-01-24 14:25 ` [PATCH 2/4] KVM: arm64: pmu: Don't mark a counter as chained if the odd one is disabled Eric Auger 2020-01-24 14:25 ` Eric Auger 2020-01-24 14:25 ` [PATCH 3/4] KVM: arm64: pmu: Fix chained SW_INCR counters Eric Auger 2020-01-24 14:25 ` Eric Auger 2020-01-24 14:25 ` [PATCH 4/4] KVM: arm64: pmu: Only handle supported event counters Eric Auger 2020-01-24 14:25 ` Eric Auger
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200124142535.29386-2-eric.auger@redhat.com \ --to=eric.auger@redhat.com \ --cc=andrew.murray@arm.com \ --cc=eric.auger.pro@gmail.com \ --cc=kvmarm@lists.cs.columbia.edu \ --cc=linux-kernel@vger.kernel.org \ --cc=maz@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.