From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Cc: piotr.zdunowski@intel.com
Subject: [Intel-gfx] [RFC 2/2] drm/i915/tgl: WaDisableGPGPUMidThreadPreemption
Date: Thu, 30 Jan 2020 11:31:08 +0000 [thread overview]
Message-ID: <20200130113108.10441-2-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20200130113108.10441-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Make thread-group preemption default because...?
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: piotr.zdunowski@intel.com
Cc: michal.mrozek@intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5d2a8cb70e16..809bb56eb167 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+ /* WaDisableGPGPUMidThreadPreemption:tgl */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
static void
--
2.20.1
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next prev parent reply other threads:[~2020-01-30 11:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-30 11:31 [Intel-gfx] [RFC 1/2] drm/i915/tgl: WaEnablePreemptionGranularityControlByUMD Tvrtko Ursulin
2020-01-30 11:31 ` Tvrtko Ursulin [this message]
2020-01-30 11:34 ` Chris Wilson
2020-01-30 12:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] " Patchwork
2020-02-02 0:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-02-03 17:33 ` [Intel-gfx] [RFC 1/2] " Matt Roper
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