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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: [PATCH 22/26] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling
Date: Mon,  3 Feb 2020 17:13:39 +0200	[thread overview]
Message-ID: <20200203151343.14378-23-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add helpers to determine whether the DFP supports
YCbCr 4:2:0 passthrough or YCbCr 4:4:4->4:2:0 conversion.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 44 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |  8 ++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 507282dc79ac..66d176090d6a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -615,6 +615,50 @@ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+				       const u8 port_cap[4])
+{
+	if (!drm_dp_is_branch(dpcd))
+		return false;
+
+	if (dpcd[DP_DPCD_REV] < 0x13)
+		return false;
+
+	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+	case DP_DS_PORT_TYPE_DP:
+		return true;
+	case DP_DS_PORT_TYPE_HDMI:
+		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+			return false;
+
+		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
+	default:
+		return false;
+	}
+}
+EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
+
+bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+					     const u8 port_cap[4])
+{
+	if (!drm_dp_is_branch(dpcd))
+		return false;
+
+	if (dpcd[DP_DPCD_REV] < 0x13)
+		return false;
+
+	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+	case DP_DS_PORT_TYPE_HDMI:
+		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+			return false;
+
+		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
+	default:
+		return false;
+	}
+}
+EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
+
 /**
  * drm_dp_downstream_mode() - return a mode for downstream facing port
  * @dpcd: DisplayPort configuration data
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index be4a5ffe4252..9cef282064f3 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -406,6 +406,10 @@ struct drm_device;
 # define DP_DS_DVI_HIGH_COLOR_DEPTH	    (1 << 2)
 /* offset 3 for HDMI */
 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
+# define DP_DS_HDMI_YCBCR422_PASS_THROUGH   (1 << 1)
+# define DP_DS_HDMI_YCBCR420_PASS_THROUGH   (1 << 2)
+# define DP_DS_HDMI_YCBCR444_TO_422_CONV    (1 << 3)
+# define DP_DS_HDMI_YCBCR444_TO_420_CONV    (1 << 4)
 
 #define DP_MAX_DOWNSTREAM_PORTS		    0x10
 
@@ -1500,6 +1504,10 @@ int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 			      const u8 port_cap[4],
 			      const struct edid *edid);
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+				       const u8 port_cap[4]);
+bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+					     const u8 port_cap[4]);
 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
 						const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 						const u8 port_cap[4]);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 22/26] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling
Date: Mon,  3 Feb 2020 17:13:39 +0200	[thread overview]
Message-ID: <20200203151343.14378-23-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add helpers to determine whether the DFP supports
YCbCr 4:2:0 passthrough or YCbCr 4:4:4->4:2:0 conversion.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 44 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |  8 ++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 507282dc79ac..66d176090d6a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -615,6 +615,50 @@ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+				       const u8 port_cap[4])
+{
+	if (!drm_dp_is_branch(dpcd))
+		return false;
+
+	if (dpcd[DP_DPCD_REV] < 0x13)
+		return false;
+
+	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+	case DP_DS_PORT_TYPE_DP:
+		return true;
+	case DP_DS_PORT_TYPE_HDMI:
+		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+			return false;
+
+		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
+	default:
+		return false;
+	}
+}
+EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
+
+bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+					     const u8 port_cap[4])
+{
+	if (!drm_dp_is_branch(dpcd))
+		return false;
+
+	if (dpcd[DP_DPCD_REV] < 0x13)
+		return false;
+
+	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+	case DP_DS_PORT_TYPE_HDMI:
+		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+			return false;
+
+		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
+	default:
+		return false;
+	}
+}
+EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
+
 /**
  * drm_dp_downstream_mode() - return a mode for downstream facing port
  * @dpcd: DisplayPort configuration data
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index be4a5ffe4252..9cef282064f3 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -406,6 +406,10 @@ struct drm_device;
 # define DP_DS_DVI_HIGH_COLOR_DEPTH	    (1 << 2)
 /* offset 3 for HDMI */
 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
+# define DP_DS_HDMI_YCBCR422_PASS_THROUGH   (1 << 1)
+# define DP_DS_HDMI_YCBCR420_PASS_THROUGH   (1 << 2)
+# define DP_DS_HDMI_YCBCR444_TO_422_CONV    (1 << 3)
+# define DP_DS_HDMI_YCBCR444_TO_420_CONV    (1 << 4)
 
 #define DP_MAX_DOWNSTREAM_PORTS		    0x10
 
@@ -1500,6 +1504,10 @@ int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 			      const u8 port_cap[4],
 			      const struct edid *edid);
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+				       const u8 port_cap[4]);
+bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+					     const u8 port_cap[4]);
 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
 						const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 						const u8 port_cap[4]);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2020-02-03 15:14 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-03 15:13 [PATCH 00/26] drm/i915: Pimp DP DFP handling Ville Syrjala
2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 01/26] drm/i915: Nuke pre-production GLK HDMI w/a 1139 Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 02/26] drm/i915: Limit display Wa_1405510057 to gen11 Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 03/26] drm/i915: Drop WaDDIIOTimeout:glk Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 04/26] drm/i915: Add glk to intel_detect_preproduction_hw() Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 05/26] drm/dp: Include the AUX CH name in the debug messages Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 06/26] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 07/26] drm/dp: Define protocol converter DPCD registers Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 08/26] drm/dp: Define more downstream facing port caps Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 09/26] drm/i915: Reworkd DFP max bpc handling Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 10/26] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 11/26] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 12/26] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 13/26] drm/i915: Reworkd DP DFP clock handling Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 14/26] drm/i915: Dump downstream facing port caps Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala
2020-02-03 15:13 ` [PATCH 16/26] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 17/26] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 18/26] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 19/26] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 20/26] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 21/26] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` Ville Syrjala [this message]
2020-02-03 15:13   ` [Intel-gfx] [PATCH 22/26] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala
2020-02-03 15:13 ` [PATCH 23/26] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 24/26] drm/i915: Decouple DP++ from the HDMI code Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 25/26] drm/i915: Try to probe DP++ dongles on DP++ downstream facing ports Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-03 15:13 ` [PATCH 26/26] drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on DP DFPs Ville Syrjala
2020-02-03 15:13   ` [Intel-gfx] " Ville Syrjala
2020-02-04 19:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Pimp DP DFP handling Patchwork

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