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From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org
Subject: [kvm-unit-tests PATCH 3/4] nVMX: Mark bit 39 of MSR_IA32_VMX_EPT_VPID_CAP as reserved
Date: Fri,  7 Feb 2020 09:42:43 -0800	[thread overview]
Message-ID: <20200207174244.6590-4-sean.j.christopherson@intel.com> (raw)
In-Reply-To: <20200207174244.6590-1-sean.j.christopherson@intel.com>

Remove bit 39, which is defined as reserved in Intel's SDM, from the set
of allowed-1 bits in MSR_IA32_VMX_EPT_VPID_CAP.

Fixes: 69c8d31 ("VMX: Validate capability MSRs")
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
 x86/vmx.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/x86/vmx.c b/x86/vmx.c
index 3a99d27..ac4aa56 100644
--- a/x86/vmx.c
+++ b/x86/vmx.c
@@ -1550,7 +1550,6 @@ static void test_vmx_caps(void)
 		    EPT_CAP_INVEPT_SINGLE |
 		    EPT_CAP_INVEPT_ALL |
 		    VPID_CAP_INVVPID |
-		    (1ull << 39) |
 		    VPID_CAP_INVVPID_ADDR |
 		    VPID_CAP_INVVPID_CXTGLB |
 		    VPID_CAP_INVVPID_ALL |
-- 
2.24.1


  parent reply	other threads:[~2020-02-07 17:42 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-07 17:42 [kvm-unit-tests PATCH 0/4] nVMX: 5-level nested EPT support Sean Christopherson
2020-02-07 17:42 ` [kvm-unit-tests PATCH 1/4] nVMX: Extend EPTP test to allow 5-level EPT Sean Christopherson
2020-02-07 17:42 ` [kvm-unit-tests PATCH 2/4] nVMX: Refactor the EPT/VPID MSR cap check to make it readable Sean Christopherson
2020-02-07 17:42 ` Sean Christopherson [this message]
2020-02-07 17:42 ` [kvm-unit-tests PATCH 4/4] nVMX: Extend EPT cap MSR test to allow 5-level EPT Sean Christopherson
2020-06-22 17:42 ` [kvm-unit-tests PATCH 0/4] nVMX: 5-level nested EPT support Sean Christopherson
2020-06-22 17:44   ` Paolo Bonzini

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