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From: Rafael Antognolli <rafael.antognolli@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1808121037 to tgl.
Date: Wed, 12 Feb 2020 11:17:28 -0800	[thread overview]
Message-ID: <20200212191728.25227-1-rafael.antognolli@intel.com> (raw)

It's not clear whether this workaround is final yet, but the BSpec
indicates that userspace needs to set bit 9 of this register on demand:

   "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
   Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"

BugLink: https://gitlab.freedesktop.org/mesa/mesa/issues/2501
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 62b43f538a56..57b9685d9347 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1264,6 +1264,12 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
 				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
 				  RING_FORCE_TO_NONPRIV_RANGE_4);
+
+		/* Wa_1808121037:tgl
+		 *
+		 * Allow userpace to implement this workaround.
+		 */
+		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
 		break;
 	default:
 		break;
-- 
2.25.0

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             reply	other threads:[~2020-02-12 19:17 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-12 19:17 Rafael Antognolli [this message]
2020-02-13  7:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_1808121037 to tgl Patchwork
2020-02-14 17:10 ` [Intel-gfx] [PATCH] " Matt Roper
2020-02-14 17:24   ` Rafael Antognolli
2020-02-17  3:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
2020-02-18 18:06   ` Matt Roper

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