[Intel-gfx] [PATCH v1 2/2] drm/i915: Update dbuf slices also when active_pipe_changes pending

[Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>]

When distrust_bios_wm flag is set, we might have active_pipe_changes
flag set which forces ddb recalculation in absence of state->modeset
field being set. Which might in turn result in inconsistent update,
i.e ddb/wm allocations are updated in hw, but DBuf slice power state
is not. Fix this by evaluating active_pipe_changes field as well,
as it currently behaves as a separate entity in the code from
state->modeset.
Previously with Ville we tried to fix that by forcing a modeset
when distrust_bios_wm is set, however it broke DSI code as it
didn't have pipe_config precomputed, so this fix probably is more
preferrable.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 61ba1f2256a0..6eee69f8464a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15723,7 +15723,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		intel_encoders_update_prepare(state);
 
 	/* Enable all new slices, we might need */
-	if (state->modeset)
+	if (state->modeset || state->active_pipe_changes)
 		icl_dbuf_slice_pre_update(state);
 
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -15780,7 +15780,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	}
 
 	/* Disable all slices, we don't need */
-	if (state->modeset)
+	if (state->modeset || state->active_pipe_changes)
 		icl_dbuf_slice_post_update(state);
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-- 
2.24.1.485.gad05a3d8e5

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