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From: David Gibson <david@gibson.dropbear.id.au>
To: groug@kaod.org, clg@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org
Cc: Laurent Vivier <lvivier@redhat.com>,
	qemu-ppc@nongnu.org, Thomas Huth <thuth@redhat.com>,
	Xiao Guangrong <xiaoguangrong.eric@gmail.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	aik@ozlabs.ru, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	paulus@samba.org, Paolo Bonzini <pbonzini@redhat.com>,
	Igor Mammedov <imammedo@redhat.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [PATCH v4 00/12] target/ppc: Correct some errors with real mode handling
Date: Wed, 19 Feb 2020 13:13:57 +1100	[thread overview]
Message-ID: <20200219021409.21332-1-david@gibson.dropbear.id.au> (raw)

POWER "book S" (server class) cpus have a concept of "real mode" where
MMU translation is disabled... sort of.  In fact this can mean a bunch
of slightly different things when hypervisor mode and other
considerations are present.

We had some errors in edge cases here, so clean some things up and
correct them.

Changes since v3:
 * Fix style errors reported by checkpatch
Changes since v2:
 * Removed 32-bit hypervisor stubs more completely
 * Minor polish based on review comments
Changes since RFCv1:
 * Add a number of extra patches taking advantage of the initial
   cleanups

David Gibson (12):
  ppc: Remove stub support for 32-bit hypervisor mode
  ppc: Remove stub of PPC970 HID4 implementation
  target/ppc: Correct handling of real mode accesses with vhyp on hash
    MMU
  target/ppc: Introduce ppc_hash64_use_vrma() helper
  spapr, ppc: Remove VPM0/RMLS hacks for POWER9
  target/ppc: Remove RMOR register from POWER9 & POWER10
  target/ppc: Use class fields to simplify LPCR masking
  target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]
  target/ppc: Correct RMLS table
  target/ppc: Only calculate RMLS derived RMA limit on demand
  target/ppc: Streamline construction of VRMA SLB entry
  target/ppc: Don't store VRMA SLBE persistently

 hw/ppc/spapr_cpu_core.c         |   6 +-
 target/ppc/cpu-qom.h            |   1 +
 target/ppc/cpu.h                |  25 +--
 target/ppc/mmu-hash64.c         | 331 ++++++++++++--------------------
 target/ppc/translate_init.inc.c |  63 ++++--
 5 files changed, 179 insertions(+), 247 deletions(-)

-- 
2.24.1



             reply	other threads:[~2020-02-19  2:15 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-19  2:13 David Gibson [this message]
2020-02-19  2:13 ` [PATCH v4 01/12] ppc: Remove stub support for 32-bit hypervisor mode David Gibson
2020-02-19  2:13 ` [PATCH v4 02/12] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-02-19  2:14 ` [PATCH v4 03/12] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-02-19  2:14 ` [PATCH v4 04/12] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-02-19  2:14 ` [PATCH v4 05/12] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-02-19  2:14 ` [PATCH v4 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-02-19  2:14 ` [PATCH v4 07/12] target/ppc: Use class fields to simplify LPCR masking David Gibson
2020-02-19  2:14 ` [PATCH v4 08/12] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-02-19  2:14 ` [PATCH v4 09/12] target/ppc: Correct RMLS table David Gibson
2020-02-19  2:14 ` [PATCH v4 10/12] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-02-19  2:14 ` [PATCH v4 11/12] target/ppc: Streamline construction of VRMA SLB entry David Gibson
2020-02-19  2:14 ` [PATCH v4 12/12] target/ppc: Don't store VRMA SLBE persistently David Gibson

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