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From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Cc: Maxime Ripard <mripard@kernel.org>,
	Robert Richter <rric@kernel.org>,
	soc@kernel.org, Jon Loeliger <jdl@jdl.com>,
	Mark Langsdorf <mlangsdo@redhat.com>,
	Eric Auger <eric.auger@redhat.com>, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH v2 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema
Date: Thu, 27 Feb 2020 18:22:06 +0000	[thread overview]
Message-ID: <20200227182210.89512-10-andre.przywara@arm.com> (raw)
In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com>

Convert the L2-ECC controller binding to DT schema format using
json-schema.
This is indented to be just used for error reporting.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 -------
 .../bindings/arm/calxeda/l2ecc.yaml           | 43 +++++++++++++++++++
 2 files changed, 43 insertions(+), 15 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml

diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
deleted file mode 100644
index 94e642a33db0..000000000000
--- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Calxeda Highbank L2 cache ECC
-
-Properties:
-- compatible : Should be "calxeda,hb-sregs-l2-ecc"
-- reg : Address and size for ECC error interrupt clear registers.
-- interrupts : Should be single bit error interrupt, then double bit error
-	interrupt.
-
-Example:
-
-	sregs@fff3c200 {
-		compatible = "calxeda,hb-sregs-l2-ecc";
-		reg = <0xfff3c200 0x100>;
-		interrupts = <0 71 4  0 72 4>;
-	};
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
new file mode 100644
index 000000000000..5481dd7216ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda Highbank L2 cache ECC
+
+description: |
+  Binding for the Calxeda Highbank L2 cache controller ECC device.
+  This does not cover the actual L2 cache controller control registers,
+  but just the error reporting functionality.
+
+maintainers:
+  - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+  compatible:
+    const: "calxeda,hb-sregs-l2-ecc"
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: |
+      Should be single bit error interrupt, then double bit error interrupt.
+    minItems: 2
+    maxItems: 2
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    sregs@fff3c200 {
+        compatible = "calxeda,hb-sregs-l2-ecc";
+        reg = <0xfff3c200 0x100>;
+        interrupts = <0 71 4>, <0 72 4>;
+    };
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Cc: Jon Loeliger <jdl@jdl.com>, Mark Langsdorf <mlangsdo@redhat.com>,
	Robert Richter <rric@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Maxime Ripard <mripard@kernel.org>,
	Eric Auger <eric.auger@redhat.com>,
	soc@kernel.org, Will Deacon <will@kernel.org>
Subject: [PATCH v2 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema
Date: Thu, 27 Feb 2020 18:22:06 +0000	[thread overview]
Message-ID: <20200227182210.89512-10-andre.przywara@arm.com> (raw)
In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com>

Convert the L2-ECC controller binding to DT schema format using
json-schema.
This is indented to be just used for error reporting.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 -------
 .../bindings/arm/calxeda/l2ecc.yaml           | 43 +++++++++++++++++++
 2 files changed, 43 insertions(+), 15 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml

diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
deleted file mode 100644
index 94e642a33db0..000000000000
--- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Calxeda Highbank L2 cache ECC
-
-Properties:
-- compatible : Should be "calxeda,hb-sregs-l2-ecc"
-- reg : Address and size for ECC error interrupt clear registers.
-- interrupts : Should be single bit error interrupt, then double bit error
-	interrupt.
-
-Example:
-
-	sregs@fff3c200 {
-		compatible = "calxeda,hb-sregs-l2-ecc";
-		reg = <0xfff3c200 0x100>;
-		interrupts = <0 71 4  0 72 4>;
-	};
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
new file mode 100644
index 000000000000..5481dd7216ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda Highbank L2 cache ECC
+
+description: |
+  Binding for the Calxeda Highbank L2 cache controller ECC device.
+  This does not cover the actual L2 cache controller control registers,
+  but just the error reporting functionality.
+
+maintainers:
+  - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+  compatible:
+    const: "calxeda,hb-sregs-l2-ecc"
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: |
+      Should be single bit error interrupt, then double bit error interrupt.
+    minItems: 2
+    maxItems: 2
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    sregs@fff3c200 {
+        compatible = "calxeda,hb-sregs-l2-ecc";
+        reg = <0xfff3c200 0x100>;
+        interrupts = <0 71 4>, <0 72 4>;
+    };
-- 
2.17.1


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  parent reply	other threads:[~2020-02-27 18:22 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-27 18:21 [PATCH v2 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
2020-02-27 18:21 ` Andre Przywara
2020-02-27 18:21 ` [PATCH v2 01/13] arm: dts: calxeda: Basic DT file fixes Andre Przywara
2020-02-27 18:21   ` Andre Przywara
2020-02-27 21:42   ` Rob Herring
2020-02-27 21:42     ` Rob Herring
2020-02-27 18:21 ` [PATCH v2 02/13] arm: dts: calxeda: Provide UART clock Andre Przywara
2020-02-27 18:21   ` Andre Przywara
2020-02-27 21:43   ` Rob Herring
2020-02-27 21:43     ` Rob Herring
2020-02-27 18:22 ` [PATCH v2 03/13] arm: dts: calxeda: Fix interrupt grouping Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 21:45   ` Rob Herring
2020-02-27 21:45     ` Rob Herring
2020-02-27 18:22 ` [PATCH v2 04/13] arm: dts: calxeda: Group port-phys and sgpio-gpio items Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 21:45   ` Rob Herring
2020-02-27 21:45     ` Rob Herring
2020-02-27 18:22 ` [PATCH v2 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-28 22:20   ` Stephen Boyd
2020-02-27 18:22 ` [PATCH v2 06/13] dt-bindings: sata: Convert Calxeda SATA controller " Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 22:05   ` Rob Herring
2020-02-27 22:05     ` Rob Herring
2020-02-27 18:22 ` [PATCH v2 07/13] dt-bindings: net: Convert Calxeda Ethernet binding " Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 18:22 ` [PATCH v2 08/13] dt-bindings: phy: Convert Calxeda ComboPHY " Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 18:22 ` Andre Przywara [this message]
2020-02-27 18:22   ` [PATCH v2 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller " Andre Przywara
2020-02-27 18:22 ` [PATCH v2 10/13] dt-bindings: memory-controllers: Convert Calxeda DDR " Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 18:22 ` [PATCH v2 11/13] dt-bindings: ipmi: Convert IPMI-SMIC bindings " Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 22:21   ` Rob Herring
2020-02-27 22:21     ` Rob Herring
2020-02-28  0:21     ` André Przywara
2020-02-28  0:21       ` André Przywara
2020-02-27 18:22 ` [PATCH v2 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 22:22   ` Rob Herring
2020-02-27 22:22     ` Rob Herring
2020-02-27 18:22 ` [PATCH v2 13/13] MAINTAINERS: Update Calxeda Highbank maintainership Andre Przywara
2020-02-27 18:22   ` Andre Przywara
2020-02-27 22:35   ` Rob Herring
2020-02-27 22:35     ` Rob Herring
2020-02-28  0:39     ` Olof Johansson
2020-02-28  0:39       ` Olof Johansson
2020-02-28 11:53       ` Andre Przywara
2020-02-28 11:53         ` Andre Przywara

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