From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Add Wa_1604278689:icl,ehl
Date: Mon, 9 Mar 2020 17:49:07 -0700 [thread overview]
Message-ID: <20200310004911.1723239-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20200310004911.1723239-1-matthew.d.roper@intel.com>
The bspec description for this workaround tells us to program
0xFFFF_FFFF into both FBC_RT_BASE_ADDR_REGISTER_* registers, but we've
previously found that this leads to failures in CI. Our suspicion is
that the failures are caused by this valid turning on the "address valid
bit" even though we're intentionally supplying an invalid address.
Experimentation has shown that setting all bits _except_ for the
RT_VALID bit seems to avoid these failures.
v2:
- Mask off the RT_VALID bit. Experimentation with CI trybot indicates
that this is necessary to avoid reset failures on BCS.
Bspec: 11388
Bspec: 33451
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3e352e2a5b79..1cf931dde0ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -575,6 +575,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
/* allow headerless messages for preemptible GPGPU context */
WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
+
+ /* Wa_1604278689:icl,ehl */
+ wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
+ 0, /* write-only register; skip validation */
+ 0xFFFFFFFF);
+ wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
}
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 79ae9654dac9..92ae96cf5b64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3285,6 +3285,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/* Framebuffer compression for Ivybridge */
#define IVB_FBC_RT_BASE _MMIO(0x7020)
+#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
#define IPS_CTL _MMIO(0x43408)
#define IPS_ENABLE (1 << 31)
--
2.24.1
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next prev parent reply other threads:[~2020-03-10 0:49 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-10 0:49 [Intel-gfx] [PATCH 0/7] Gen11 workarounds Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 1/7] drm/i915: Handle all MCR ranges Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 2/7] drm/i915: Add Wa_1207131216:icl,ehl Matt Roper
2020-03-10 16:22 ` Mika Kuoppala
2020-03-10 0:49 ` Matt Roper [this message]
2020-03-10 16:37 ` [Intel-gfx] [PATCH 3/7] drm/i915: Add Wa_1604278689:icl,ehl Chris Wilson
2020-03-10 16:49 ` Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 4/7] drm/i915: Add Wa_1406306137:icl,ehl Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 5/7] drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 6/7] drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 7/7] drm/i915: Add Wa_1409178092:icl,ehl Matt Roper
2020-03-10 1:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen11 workarounds Patchwork
2020-03-10 17:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-10 22:28 ` Souza, Jose
2020-03-10 23:18 ` Matt Roper
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