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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/3] drm: Refactor intel_dp_compute_link_config_*()
Date: Thu, 19 Mar 2020 18:38:43 +0200	[thread overview]
Message-ID: <20200319163844.22783-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200319163844.22783-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the common parts of intel_dp_compute_link_config_wide()
and intel_dp_compute_link_config_fast() into a shared helper
to avoid duplicated code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++++++++++++-----------
 1 file changed, 44 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 85abcce492ca..8491ce8b8c15 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2014,34 +2014,47 @@ static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bp
 	return bpp;
 }
 
+static bool
+intel_dp_link_config_valid(const struct intel_crtc_state *crtc_state,
+			   int bpp, int link_clock, int lane_count)
+{
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	int output_bpp = intel_dp_output_bpp(crtc_state, bpp);
+	int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
+					       output_bpp);
+	int link_avail = intel_dp_max_data_rate(link_clock, lane_count);
+
+	return mode_rate <= link_avail;
+}
+
 /* Optimize link config in order: max bpp, min clock, min lanes */
 static int
 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
-				  struct intel_crtc_state *pipe_config,
+				  struct intel_crtc_state *crtc_state,
 				  const struct link_config_limits *limits)
 {
-	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
-	int bpp, clock, lane_count;
-	int mode_rate, link_clock, link_avail;
+	int bpp;
 
 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
-		int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
+		int clock;
 
-		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
-						   output_bpp);
+		for (clock = limits->min_clock;
+		     clock <= limits->max_clock;
+		     clock++) {
+			int lane_count;
 
-		for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
 			for (lane_count = limits->min_lane_count;
 			     lane_count <= limits->max_lane_count;
 			     lane_count <<= 1) {
-				link_clock = intel_dp->common_rates[clock];
-				link_avail = intel_dp_max_data_rate(link_clock,
-								    lane_count);
+				int link_clock = intel_dp->common_rates[clock];
 
-				if (mode_rate <= link_avail) {
-					pipe_config->lane_count = lane_count;
-					pipe_config->pipe_bpp = bpp;
-					pipe_config->port_clock = link_clock;
+				if (intel_dp_link_config_valid(crtc_state, bpp,
+							       link_clock,
+							       lane_count)) {
+					crtc_state->pipe_bpp = bpp;
+					crtc_state->port_clock = link_clock;
+					crtc_state->lane_count = lane_count;
 
 					return 0;
 				}
@@ -2055,31 +2068,30 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 /* Optimize link config in order: max bpp, min lanes, min clock */
 static int
 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
-				  struct intel_crtc_state *pipe_config,
+				  struct intel_crtc_state *crtc_state,
 				  const struct link_config_limits *limits)
 {
-	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
-	int bpp, clock, lane_count;
-	int mode_rate, link_clock, link_avail;
+	int bpp;
 
 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
-		int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
-
-		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
-						   output_bpp);
+		int lane_count;
 
 		for (lane_count = limits->min_lane_count;
 		     lane_count <= limits->max_lane_count;
 		     lane_count <<= 1) {
-			for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
-				link_clock = intel_dp->common_rates[clock];
-				link_avail = intel_dp_max_data_rate(link_clock,
-								    lane_count);
-
-				if (mode_rate <= link_avail) {
-					pipe_config->lane_count = lane_count;
-					pipe_config->pipe_bpp = bpp;
-					pipe_config->port_clock = link_clock;
+			int clock;
+
+			for (clock = limits->min_clock;
+			     clock <= limits->max_clock;
+			     clock++) {
+				int link_clock = intel_dp->common_rates[clock];
+
+				if (intel_dp_link_config_valid(crtc_state, bpp,
+							       link_clock,
+							       lane_count)) {
+					crtc_state->pipe_bpp = bpp;
+					crtc_state->port_clock = link_clock;
+					crtc_state->lane_count = lane_count;
 
 					return 0;
 				}
-- 
2.24.1

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  reply	other threads:[~2020-03-19 16:38 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-19 16:38 [Intel-gfx] [PATCH 1/3] drm/i915: Try to use fast+narrow link on eDP again and fall back to the old max strategy on failure Ville Syrjala
2020-03-19 16:38 ` Ville Syrjala [this message]
2020-03-19 16:38 ` [Intel-gfx] [PATCH 3/3] drm: Constify adjusted_mode a bit Ville Syrjala
2020-03-20 18:33   ` Manasi Navare
2020-03-19 16:53 ` [Intel-gfx] [PATCH 1/3] drm/i915: Try to use fast+narrow link on eDP again and fall back to the old max strategy on failure Hans de Goede
2020-03-19 17:06   ` Ville Syrjälä
2020-03-19 17:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2020-03-19 19:52 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-19 22:20 ` [Intel-gfx] [PATCH 1/3] " Manasi Navare
2020-03-20 19:08   ` Ville Syrjälä
2020-03-20 23:17     ` Manasi Navare
2020-03-27 15:40       ` Ville Syrjälä
2020-03-27 18:09         ` Manasi Navare
2020-07-02  9:21 ` Timo Aaltonen

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