From: Andrew Jones <drjones@redhat.com> To: pbonzini@redhat.com Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Alexandru Elisei <alexandru.elisei@arm.com> Subject: [PULL kvm-unit-tests 03/39] arm64: timer: Add ISB after register writes Date: Sat, 4 Apr 2020 16:36:55 +0200 [thread overview] Message-ID: <20200404143731.208138-4-drjones@redhat.com> (raw) In-Reply-To: <20200404143731.208138-1-drjones@redhat.com> From: Alexandru Elisei <alexandru.elisei@arm.com> From ARM DDI 0487E.a glossary, the section "Context synchronization event": "All direct and indirect writes to System registers that are made before the Context synchronization event affect any instruction, including a direct read, that appears in program order after the instruction causing the Context synchronization event." The ISB instruction is a context synchronization event [1]. Add an ISB after all register writes, to make sure that the writes have been completed when we try to test their effects. [1] ARM DDI 0487E.a, section C6.2.96 Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com> --- arm/timer.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arm/timer.c b/arm/timer.c index f390e8e65d31..c6ea108cfa4b 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -41,6 +41,7 @@ static u64 read_vtimer_cval(void) static void write_vtimer_cval(u64 val) { write_sysreg(val, cntv_cval_el0); + isb(); } static s32 read_vtimer_tval(void) @@ -51,6 +52,7 @@ static s32 read_vtimer_tval(void) static void write_vtimer_tval(s32 val) { write_sysreg(val, cntv_tval_el0); + isb(); } static u64 read_vtimer_ctl(void) @@ -61,6 +63,7 @@ static u64 read_vtimer_ctl(void) static void write_vtimer_ctl(u64 val) { write_sysreg(val, cntv_ctl_el0); + isb(); } static u64 read_ptimer_counter(void) @@ -76,6 +79,7 @@ static u64 read_ptimer_cval(void) static void write_ptimer_cval(u64 val) { write_sysreg(val, cntp_cval_el0); + isb(); } static s32 read_ptimer_tval(void) @@ -86,6 +90,7 @@ static s32 read_ptimer_tval(void) static void write_ptimer_tval(s32 val) { write_sysreg(val, cntp_tval_el0); + isb(); } static u64 read_ptimer_ctl(void) @@ -96,6 +101,7 @@ static u64 read_ptimer_ctl(void) static void write_ptimer_ctl(u64 val) { write_sysreg(val, cntp_ctl_el0); + isb(); } struct timer_info { @@ -181,7 +187,6 @@ static bool test_cval_10msec(struct timer_info *info) before_timer = info->read_counter(); info->write_cval(before_timer + time_10ms); info->write_ctl(ARCH_TIMER_CTL_ENABLE); - isb(); /* Wait for the timer to fire */ while (!(info->read_ctl() & ARCH_TIMER_CTL_ISTATUS)) @@ -217,11 +222,9 @@ static void test_timer(struct timer_info *info) /* Enable the timer, but schedule it for much later */ info->write_cval(later); info->write_ctl(ARCH_TIMER_CTL_ENABLE); - isb(); report(!gic_timer_pending(info), "not pending before"); info->write_cval(now - 1); - isb(); report(gic_timer_pending(info), "interrupt signal pending"); /* Disable the timer again and prepare to take interrupts */ -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <drjones@redhat.com> To: pbonzini@redhat.com Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PULL kvm-unit-tests 03/39] arm64: timer: Add ISB after register writes Date: Sat, 4 Apr 2020 16:36:55 +0200 [thread overview] Message-ID: <20200404143731.208138-4-drjones@redhat.com> (raw) In-Reply-To: <20200404143731.208138-1-drjones@redhat.com> From: Alexandru Elisei <alexandru.elisei@arm.com> From ARM DDI 0487E.a glossary, the section "Context synchronization event": "All direct and indirect writes to System registers that are made before the Context synchronization event affect any instruction, including a direct read, that appears in program order after the instruction causing the Context synchronization event." The ISB instruction is a context synchronization event [1]. Add an ISB after all register writes, to make sure that the writes have been completed when we try to test their effects. [1] ARM DDI 0487E.a, section C6.2.96 Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com> --- arm/timer.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arm/timer.c b/arm/timer.c index f390e8e65d31..c6ea108cfa4b 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -41,6 +41,7 @@ static u64 read_vtimer_cval(void) static void write_vtimer_cval(u64 val) { write_sysreg(val, cntv_cval_el0); + isb(); } static s32 read_vtimer_tval(void) @@ -51,6 +52,7 @@ static s32 read_vtimer_tval(void) static void write_vtimer_tval(s32 val) { write_sysreg(val, cntv_tval_el0); + isb(); } static u64 read_vtimer_ctl(void) @@ -61,6 +63,7 @@ static u64 read_vtimer_ctl(void) static void write_vtimer_ctl(u64 val) { write_sysreg(val, cntv_ctl_el0); + isb(); } static u64 read_ptimer_counter(void) @@ -76,6 +79,7 @@ static u64 read_ptimer_cval(void) static void write_ptimer_cval(u64 val) { write_sysreg(val, cntp_cval_el0); + isb(); } static s32 read_ptimer_tval(void) @@ -86,6 +90,7 @@ static s32 read_ptimer_tval(void) static void write_ptimer_tval(s32 val) { write_sysreg(val, cntp_tval_el0); + isb(); } static u64 read_ptimer_ctl(void) @@ -96,6 +101,7 @@ static u64 read_ptimer_ctl(void) static void write_ptimer_ctl(u64 val) { write_sysreg(val, cntp_ctl_el0); + isb(); } struct timer_info { @@ -181,7 +187,6 @@ static bool test_cval_10msec(struct timer_info *info) before_timer = info->read_counter(); info->write_cval(before_timer + time_10ms); info->write_ctl(ARCH_TIMER_CTL_ENABLE); - isb(); /* Wait for the timer to fire */ while (!(info->read_ctl() & ARCH_TIMER_CTL_ISTATUS)) @@ -217,11 +222,9 @@ static void test_timer(struct timer_info *info) /* Enable the timer, but schedule it for much later */ info->write_cval(later); info->write_ctl(ARCH_TIMER_CTL_ENABLE); - isb(); report(!gic_timer_pending(info), "not pending before"); info->write_cval(now - 1); - isb(); report(gic_timer_pending(info), "interrupt signal pending"); /* Disable the timer again and prepare to take interrupts */ -- 2.25.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-04-04 14:37 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-04 14:36 [PULL kvm-unit-tests 00/39] arm/arm64: The old and new Andrew Jones 2020-04-04 14:36 ` Andrew Jones 2020-04-04 14:36 ` [PULL kvm-unit-tests 01/39] Makefile: Use no-stack-protector compiler options Andrew Jones 2020-04-04 14:36 ` Andrew Jones 2020-04-04 14:36 ` [PULL kvm-unit-tests 02/39] arm/arm64: psci: Don't run C code without stack or vectors Andrew Jones 2020-04-04 14:36 ` Andrew Jones 2020-04-04 14:36 ` Andrew Jones [this message] 2020-04-04 14:36 ` [PULL kvm-unit-tests 03/39] arm64: timer: Add ISB after register writes Andrew Jones 2020-04-04 14:36 ` [PULL kvm-unit-tests 04/39] arm64: timer: Add ISB before reading the counter value Andrew Jones 2020-04-04 14:36 ` Andrew Jones 2020-04-04 14:36 ` [PULL kvm-unit-tests 05/39] arm64: timer: Make irq_received volatile Andrew Jones 2020-04-04 14:36 ` Andrew Jones 2020-04-04 14:36 ` [PULL kvm-unit-tests 06/39] arm64: timer: EOIR the interrupt after masking the timer Andrew Jones 2020-04-04 14:36 ` Andrew Jones 2020-04-04 14:36 ` [PULL kvm-unit-tests 07/39] arm64: timer: Wait for the GIC to sample timer interrupt state Andrew Jones 2020-04-04 14:36 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 08/39] arm64: timer: Check the " Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 09/39] arm64: timer: Test behavior when timer disabled or masked Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 10/39] arm/arm64: Perform dcache clean + invalidate after turning MMU off Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 11/39] arm/arm64: gic: Move gic_state enumeration to asm/gic.h Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 12/39] arm64: timer: Use the proper RDist register name in GICv3 Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 13/39] arm64: timer: Use existing helpers to access counter/timers Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 14/39] arm64: timer: Speed up gic-timer-state check Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 15/39] arm64: Provide read/write_sysreg_s Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 16/39] arm: pmu: Let pmu tests take a sub-test parameter Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 17/39] arm: pmu: Don't check PMCR.IMP anymore Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 18/39] arm: pmu: Add a pmu struct Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 19/39] arm: pmu: Introduce defines for PMU versions Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 20/39] arm: pmu: Check Required Event Support Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 21/39] arm: pmu: Basic event counter Tests Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 22/39] arm: pmu: Test SW_INCR event count Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 23/39] arm: pmu: Test chained counters Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 24/39] arm: pmu: test 32-bit <-> 64-bit transitions Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 25/39] arm: gic: Introduce gic_irq_set_clr_enable() helper Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 26/39] arm: pmu: Test overflow interrupts Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 27/39] libcflat: Add other size defines Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 28/39] page_alloc: Introduce get_order() Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 29/39] arm/arm64: gic: Introduce setup_irq() helper Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 30/39] arm/arm64: gicv3: Add some re-distributor defines Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 31/39] arm/arm64: gicv3: Set the LPI config and pending tables Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 32/39] arm/arm64: ITS: Introspection tests Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 33/39] arm/arm64: ITS: its_enable_defaults Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 34/39] arm/arm64: ITS: Device and collection Initialization Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 35/39] arm/arm64: ITS: Commands Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 36/39] arm/arm64: ITS: INT functional tests Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 37/39] arm/run: Allow Migration tests Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 38/39] arm/arm64: ITS: migration tests Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-04 14:37 ` [PULL kvm-unit-tests 39/39] arm/arm64: ITS: pending table migration test Andrew Jones 2020-04-04 14:37 ` Andrew Jones 2020-04-07 15:28 ` [PULL kvm-unit-tests 00/39] arm/arm64: The old and new Paolo Bonzini 2020-04-07 15:28 ` Paolo Bonzini
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