From: "Clément Péron" <peron.clem@gmail.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi <linux-sunxi@googlegroups.com>, "Ondrej Jirman" <megous@megous.com>, "Clément Péron" <peron.clem@gmail.com> Subject: [PATCH 4/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Date: Sun, 5 Apr 2020 12:49:10 +0200 [thread overview] Message-ID: <20200405104913.22806-5-peron.clem@gmail.com> (raw) In-Reply-To: <20200405104913.22806-1-peron.clem@gmail.com> From: Ondrej Jirman <megous@megous.com> Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the H6. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> --- .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 + 2 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi new file mode 100644 index 000000000000..b480c33f426b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com> + +/ { + cpu0_opp_table: opp_table0 { + compatible = "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp@480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <880000>; + opp-microvolt-speed2 = <880000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1000000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <940000>; + }; + + opp@1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + + opp-microvolt-speed0 = <1060000>; + opp-microvolt-speed1 = <1000000>; + opp-microvolt-speed2 = <1000000>; + }; + + opp@1800000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1800000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1100000>; + opp-microvolt-speed2 = <1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index c3e4f09f60ce..a9304fec245c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -253,6 +253,10 @@ #address-cells = <1>; #size-cells = <1>; + speedbin_efuse: speed@1c { + reg = <0x1c 0x4>; + }; + ths_calibration: thermal-sensor-calibration@14 { reg = <0x14 0x8>; }; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: "Clément Péron" <peron.clem@gmail.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org> Cc: "Ondrej Jirman" <megous@megous.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi <linux-sunxi@googlegroups.com>, "Clément Péron" <peron.clem@gmail.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Date: Sun, 5 Apr 2020 12:49:10 +0200 [thread overview] Message-ID: <20200405104913.22806-5-peron.clem@gmail.com> (raw) In-Reply-To: <20200405104913.22806-1-peron.clem@gmail.com> From: Ondrej Jirman <megous@megous.com> Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the H6. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> --- .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 + 2 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi new file mode 100644 index 000000000000..b480c33f426b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com> + +/ { + cpu0_opp_table: opp_table0 { + compatible = "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp@480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <880000>; + opp-microvolt-speed2 = <880000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1000000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <940000>; + }; + + opp@1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + + opp-microvolt-speed0 = <1060000>; + opp-microvolt-speed1 = <1000000>; + opp-microvolt-speed2 = <1000000>; + }; + + opp@1800000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1800000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1100000>; + opp-microvolt-speed2 = <1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index c3e4f09f60ce..a9304fec245c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -253,6 +253,10 @@ #address-cells = <1>; #size-cells = <1>; + speedbin_efuse: speed@1c { + reg = <0x1c 0x4>; + }; + ths_calibration: thermal-sensor-calibration@14 { reg = <0x14 0x8>; }; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-05 10:49 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-05 10:49 [PATCH 0/7] Add support for Allwinner H6 DVFS Clément Péron 2020-04-05 10:49 ` Clément Péron 2020-04-05 10:49 ` [PATCH 1/7] arm64: dts: allwinner: h6: Add clock to CPU cores Clément Péron 2020-04-05 10:49 ` Clément Péron 2020-04-05 10:49 ` [PATCH 2/7] arm64: dts: allwinner: h6: Add thermal trip points/cooling map Clément Péron 2020-04-05 10:49 ` Clément Péron 2020-04-05 10:49 ` [PATCH 3/7] arm64: dts: allwinner: h6: set thermal polling time Clément Péron 2020-04-05 10:49 ` Clément Péron 2020-04-05 11:24 ` [linux-sunxi] " Ondřej Jirman 2020-04-05 11:24 ` Ondřej Jirman 2020-04-05 14:35 ` Clément Péron 2020-04-05 14:35 ` Clément Péron 2020-04-05 10:49 ` Clément Péron [this message] 2020-04-05 10:49 ` [PATCH 4/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Clément Péron 2020-04-05 10:49 ` [PATCH 5/7] arm64: dts: allwinner: h6: Add GPU " Clément Péron 2020-04-05 10:49 ` Clément Péron 2020-04-05 10:49 ` [PATCH 6/7] arm64: configs: Enable sun50i cpufreq nvmem Clément Péron 2020-04-05 10:49 ` Clément Péron 2020-04-05 10:49 ` [PATCH 7/7] arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink GS1 Clément Péron 2020-04-05 10:49 ` Clément Péron 2020-04-05 11:31 ` [linux-sunxi] " Ondřej Jirman 2020-04-05 11:31 ` Ondřej Jirman 2020-04-05 11:51 ` [linux-sunxi] [PATCH 0/7] Add support for Allwinner H6 DVFS Ondřej Jirman 2020-04-05 11:51 ` Ondřej Jirman 2020-04-05 14:33 ` Clément Péron 2020-04-05 14:33 ` Clément Péron 2020-04-05 14:54 ` Ondřej Jirman 2020-04-05 14:54 ` Ondřej Jirman 2020-04-05 15:01 ` Clément Péron 2020-04-05 15:01 ` Clément Péron 2020-04-05 15:30 ` Clément Péron 2020-04-05 15:30 ` Clément Péron
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