From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, ankit.k.nautiyal@intel.com
Subject: [Intel-gfx] [PATCH v4 1/4] drm/i915: Power well id for ICL PG3
Date: Thu, 9 Apr 2020 11:36:43 +0530 [thread overview]
Message-ID: <20200409060646.30817-2-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20200409060646.30817-1-anshuman.gupta@intel.com>
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 433e5a81dd4d..3672c00be94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
/* Power wells at this level and above must be disabled for DC5 entry */
if (INTEL_GEN(dev_priv) >= 12)
- high_pg = TGL_DISP_PW_3;
+ high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3571,7 +3571,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3949,7 +3949,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "power well 3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = TGL_DISP_PW_3,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..56cbae6327b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,7 +100,7 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
- TGL_DISP_PW_3,
+ ICL_DISP_PW_3,
SKL_DISP_DC_OFF,
};
--
2.26.0
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next prev parent reply other threads:[~2020-04-09 6:35 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-09 6:06 [Intel-gfx] [PATCH v4 0/4] i915 lpsp support for lpsp igt Anshuman Gupta
2020-04-09 6:06 ` Anshuman Gupta [this message]
2020-04-14 14:22 ` [Intel-gfx] [PATCH v4 1/4] drm/i915: Power well id for ICL PG3 Manna, Animesh
2020-04-09 6:06 ` [Intel-gfx] [PATCH v4 2/4] drm/i915: Add i915_lpsp_capability debugfs Anshuman Gupta
2020-04-14 15:46 ` Manna, Animesh
2020-04-14 16:42 ` Anshuman Gupta
2020-04-15 12:50 ` Anshuman Gupta
2020-04-09 6:06 ` [Intel-gfx] [PATCH v4 3/4] drm/i915: Add connector dbgfs for all connectors Anshuman Gupta
2020-04-09 6:06 ` [Intel-gfx] [PATCH v4 4/4] drm/i915: Add i915_lpsp_status debugfs attribute Anshuman Gupta
2020-04-14 16:13 ` Manna, Animesh
2020-04-09 7:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for i915 lpsp support for lpsp igt (rev7) Patchwork
2020-04-10 3:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-04-15 15:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for i915 lpsp support for lpsp igt (rev8) Patchwork
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