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From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [Intel-gfx] [PATCH v22 03/13] drm/i915: Introduce skl_plane_wm_level accessor.
Date: Thu,  9 Apr 2020 18:47:20 +0300	[thread overview]
Message-ID: <20200409154730.18568-4-stanislav.lisovskiy@intel.com> (raw)
In-Reply-To: <20200409154730.18568-1-stanislav.lisovskiy@intel.com>

For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.

So this accessor will give additional flexibility
to do that.

Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.

v2: - plane_id -> plane->id(Ville Syrjälä)
    - Moved wm_level var to have more local scope
      (Ville Syrjälä)
    - Renamed yuv to color_plane(Ville Syrjälä) in
      skl_plane_wm_level

v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
    - Changed colorplane id type from boolean to int as index
      (Ville Syrjälä)
    - Moved crtc_state param so that it is first now
      (Ville Syrjälä)
    - Moved wm_level declaration to tigher scope in
      skl_write_plane_wm(Ville Syrjälä)

v4: - Started to use enum values for color plane
    - Do sizeof for a type what we are memset'ing
    - Zero out wm_uv as well(Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 85 ++++++++++++++++++++++++++-------
 1 file changed, 67 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 176a28d71822..15ad6a73e0bd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4549,6 +4549,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 	return total_data_rate;
 }
 
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+		   enum plane_id plane_id,
+		   int level,
+		   enum color_plane color_plane)
+{
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+
+	return color_plane == COLOR_PLANE_Y ? &wm->wm[level] : &wm->uv_wm[level];
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -4608,22 +4620,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 */
 	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
 		blocks = 0;
+
 		for_each_plane_id_on_crtc(crtc, plane_id) {
-			const struct skl_plane_wm *wm =
-				&crtc_state->wm.skl.optimal.planes[plane_id];
+			const struct skl_wm_level *wm_level;
+			const struct skl_wm_level *wm_uv_level;
+
+			wm_level = skl_plane_wm_level(crtc_state, plane_id,
+						      level, COLOR_PLANE_Y);
+			wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+							 level, COLOR_PLANE_UV);
 
 			if (plane_id == PLANE_CURSOR) {
-				if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+				if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
 					drm_WARN_ON(&dev_priv->drm,
-						    wm->wm[level].min_ddb_alloc != U16_MAX);
+						    wm_level->min_ddb_alloc != U16_MAX);
 					blocks = U32_MAX;
 					break;
 				}
 				continue;
 			}
 
-			blocks += wm->wm[level].min_ddb_alloc;
-			blocks += wm->uv_wm[level].min_ddb_alloc;
+			blocks += wm_level->min_ddb_alloc;
+			blocks += wm_uv_level->min_ddb_alloc;
 		}
 
 		if (blocks <= alloc_size) {
@@ -4646,11 +4664,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 * proportional to its relative data rate.
 	 */
 	for_each_plane_id_on_crtc(crtc, plane_id) {
-		const struct skl_plane_wm *wm =
-			&crtc_state->wm.skl.optimal.planes[plane_id];
+		const struct skl_wm_level *wm_level;
+		const struct skl_wm_level *wm_uv_level;
 		u64 rate;
 		u16 extra;
 
+		wm_level = skl_plane_wm_level(crtc_state, plane_id,
+					      level, COLOR_PLANE_Y);
+		wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+						 level, COLOR_PLANE_UV);
+
 		if (plane_id == PLANE_CURSOR)
 			continue;
 
@@ -4665,7 +4688,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+		total[plane_id] = wm_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 
@@ -4676,7 +4699,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+		uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 	}
@@ -4719,9 +4742,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 */
 	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
 		for_each_plane_id_on_crtc(crtc, plane_id) {
+			const struct skl_wm_level *wm_level;
+			const struct skl_wm_level *wm_uv_level;
 			struct skl_plane_wm *wm =
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
+			wm_level = skl_plane_wm_level(crtc_state, plane_id,
+						      level, COLOR_PLANE_Y);
+			wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+							 level, COLOR_PLANE_UV);
+
 			/*
 			 * We only disable the watermarks for each plane if
 			 * they exceed the ddb allocation of said plane. This
@@ -4734,9 +4764,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 			 *  planes must be enabled before the level will be used."
 			 * So this is actually safe to do.
 			 */
-			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
-			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
-				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+			if (wm_level->min_ddb_alloc > total[plane_id] ||
+			    wm_uv_level->min_ddb_alloc > uv_total[plane_id]) {
+				memset(&wm->wm[level], 0,
+				       sizeof(wm->wm[level]));
+				memset(&wm->uv_wm[level], 0,
+				       sizeof(wm->uv_wm[level]));
+			}
 
 			/*
 			 * Wa_1408961008:icl, ehl
@@ -4744,9 +4778,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 			 */
 			if (IS_GEN(dev_priv, 11) &&
 			    level == 1 && wm->wm[0].plane_en) {
-				wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
-				wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
-				wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+				wm_level = skl_plane_wm_level(crtc_state, plane_id,
+							      0, COLOR_PLANE_Y);
+				wm->wm[level].plane_res_b =
+					wm_level->plane_res_b;
+				wm->wm[level].plane_res_l =
+					wm_level->plane_res_l;
+				wm->wm[level].ignore_lines =
+					wm_level->ignore_lines;
 			}
 		}
 	}
@@ -5360,8 +5399,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
+		const struct skl_wm_level *wm_level;
+		int color_plane = 0;
+
+		wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
@@ -5394,8 +5438,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
+		const struct skl_wm_level *wm_level;
+		int color_plane = 0;
+
+		wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
-- 
2.24.1.485.gad05a3d8e5

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  parent reply	other threads:[~2020-04-09 15:51 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-09 15:47 [Intel-gfx] [PATCH v22 00/13] SAGV support for Gen12+ Stanislav Lisovskiy
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 01/13] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-04-14 17:47   ` Ville Syrjälä
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 02/13] drm/i915: Eliminate magic numbers "0" and "1" from color plane Stanislav Lisovskiy
2020-04-14 17:36   ` Ville Syrjälä
2020-04-15  8:19     ` Lisovskiy, Stanislav
2020-04-09 15:47 ` Stanislav Lisovskiy [this message]
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 04/13] drm/i915: Add intel_atomic_get_bw_*_state helpers Stanislav Lisovskiy
2020-04-14 17:40   ` Ville Syrjälä
2020-04-15  8:14     ` Lisovskiy, Stanislav
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 05/13] drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv Stanislav Lisovskiy
2020-04-10 12:24   ` [Intel-gfx] [PATCH v23 " Stanislav Lisovskiy
2020-04-14 17:16     ` Ville Syrjälä
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 06/13] drm/i915: Add pre/post plane updates for SAGV Stanislav Lisovskiy
2020-04-14 17:42   ` Ville Syrjälä
2020-04-15  8:04     ` Lisovskiy, Stanislav
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 07/13] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
2020-04-10 12:26   ` [Intel-gfx] [PATCH v23 " Stanislav Lisovskiy
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 08/13] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
2020-04-10 12:28   ` [Intel-gfx] [PATCH v23 " Stanislav Lisovskiy
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 09/13] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
2020-04-10 12:30   ` [Intel-gfx] [PATCH v23 " Stanislav Lisovskiy
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 10/13] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 11/13] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 12/13] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-04-09 15:47 ` [Intel-gfx] [PATCH v22 13/13] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-04-09 17:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev14) Patchwork
2020-04-09 17:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-04-09 17:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-10  8:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-10 12:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for SAGV support for Gen12+ (rev18) Patchwork
2020-04-10 13:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-04-10 17:04   ` Lisovskiy, Stanislav
2020-04-11  7:26 ` Patchwork
2020-04-13  7:18   ` Lisovskiy, Stanislav
2020-04-13  8:18     ` Vudum, Lakshminarayana
2020-04-13  8:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-14  6:07 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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