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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add ICL PG3 PW ID for EHL
Date: Fri, 17 Apr 2020 22:58:35 +0530	[thread overview]
Message-ID: <20200417172835.15461-1-anshuman.gupta@intel.com> (raw)

Gen11 onwards PG3 contains functions for pipe B,
external displays, and VGA. Add missing ICL_DISP_PW_3
for ehl_power_wells.

Cc: Animesh Manna <animesh.manna@intel.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1737
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d01c79fb9db..e9ced41fe7e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -3804,7 +3804,7 @@ static const struct i915_power_well_desc ehl_power_wells[] = {
 		.name = "power well 3",
 		.domains = ICL_PW_3_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
+		.id = ICL_DISP_PW_3,
 		{
 			.hsw.regs = &hsw_power_well_regs,
 			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
-- 
2.26.0

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             reply	other threads:[~2020-04-17 17:38 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-17 17:28 Anshuman Gupta [this message]
2020-04-18  1:14 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Add ICL PG3 PW ID for EHL Patchwork
2020-04-18  1:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-18  6:44 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-04-19 21:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
2020-04-20 10:54 ` [Intel-gfx] [PATCH] " Manna, Animesh

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