From: Lars Povlsen <lars.povlsen@microchip.com> To: Mark Brown <broonie@kernel.org>, SoC Team <soc@kernel.org>, Rob Herring <robh+dt@kernel.org> Cc: Lars Povlsen <lars.povlsen@microchip.com>, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Alexandre Belloni <alexandre.belloni@bootlin.com> Subject: [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Date: Wed, 13 May 2020 16:00:27 +0200 [thread overview] Message-ID: <20200513140031.25633-7-lars.povlsen@microchip.com> (raw) In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> This add DT bindings for the Sparx5 SPI driver. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- .../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++---- 1 file changed, 39 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml index a3ac0fa576553..8beecde4b0880 100644 --- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml @@ -23,15 +23,23 @@ properties: enum: - mscc,ocelot-spi - mscc,jaguar2-spi + - microchip,sparx5-spi interrupts: maxItems: 1 reg: minItems: 2 - items: - - description: Designware SPI registers - - description: CS override registers + maxItems: 3 + oneOf: + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - description: Direct mapped SPI read area. If provided, the + driver will register spi_mem_op's to take advantage of it. clocks: maxItems: 1 @@ -43,6 +51,23 @@ properties: enum: [ 2, 4 ] maxItems: 1 + spi-rx-delay-us: + description: | + The delay (in usec) of the RX signal sample position. This can + be used to tne the RX timing in order to acheive higher + speeds. This is used for all devices on the bus. + default: 0 + maxItems: 1 + + interface-mapping-mask: + description: | + On the Sparx5 variant, two different busses are connected to the + controller. This property is a mask per chip-select, indicating + whether the CS should go to one or the other interface. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maxItems: 1 + required: - compatible - reg @@ -50,11 +75,15 @@ required: examples: - | - spi0: spi@101000 { - compatible = "mscc,ocelot-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x101000 0x100>, <0x3c 0x18>; - interrupts = <9>; - clocks = <&ahb_clk>; + #include <dt-bindings/interrupt-controller/arm-gic.h> + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Lars Povlsen <lars.povlsen@microchip.com> To: Mark Brown <broonie@kernel.org>, SoC Team <soc@kernel.org>, Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org, Alexandre Belloni <alexandre.belloni@bootlin.com>, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Lars Povlsen <lars.povlsen@microchip.com>, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Date: Wed, 13 May 2020 16:00:27 +0200 [thread overview] Message-ID: <20200513140031.25633-7-lars.povlsen@microchip.com> (raw) In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> This add DT bindings for the Sparx5 SPI driver. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- .../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++---- 1 file changed, 39 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml index a3ac0fa576553..8beecde4b0880 100644 --- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml @@ -23,15 +23,23 @@ properties: enum: - mscc,ocelot-spi - mscc,jaguar2-spi + - microchip,sparx5-spi interrupts: maxItems: 1 reg: minItems: 2 - items: - - description: Designware SPI registers - - description: CS override registers + maxItems: 3 + oneOf: + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - description: Direct mapped SPI read area. If provided, the + driver will register spi_mem_op's to take advantage of it. clocks: maxItems: 1 @@ -43,6 +51,23 @@ properties: enum: [ 2, 4 ] maxItems: 1 + spi-rx-delay-us: + description: | + The delay (in usec) of the RX signal sample position. This can + be used to tne the RX timing in order to acheive higher + speeds. This is used for all devices on the bus. + default: 0 + maxItems: 1 + + interface-mapping-mask: + description: | + On the Sparx5 variant, two different busses are connected to the + controller. This property is a mask per chip-select, indicating + whether the CS should go to one or the other interface. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maxItems: 1 + required: - compatible - reg @@ -50,11 +75,15 @@ required: examples: - | - spi0: spi@101000 { - compatible = "mscc,ocelot-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x101000 0x100>, <0x3c 0x18>; - interrupts = <9>; - clocks = <&ahb_clk>; + #include <dt-bindings/interrupt-controller/arm-gic.h> + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.26.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-05-13 14:01 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-13 14:00 [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:20 ` Mark Brown 2020-05-14 13:04 ` Serge Semin 2020-05-14 13:04 ` Serge Semin 2020-05-15 9:11 ` Lars Povlsen 2020-05-15 9:11 ` Lars Povlsen 2020-05-13 14:37 ` Mark Brown 2020-05-19 10:21 ` Lars Povlsen 2020-05-19 10:21 ` Lars Povlsen 2020-05-13 14:55 ` Andy Shevchenko 2020-05-13 14:55 ` Andy Shevchenko 2020-05-19 10:25 ` Lars Povlsen 2020-05-19 10:25 ` Lars Povlsen 2020-06-02 19:10 ` Serge Semin 2020-06-02 19:10 ` Serge Semin 2020-06-09 9:13 ` Lars Povlsen 2020-06-09 9:13 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 02/10] spi: dw: Add support for RX sample delay register Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-06-02 19:39 ` Serge Semin 2020-06-02 19:39 ` Serge Semin 2020-06-09 10:04 ` Lars Povlsen 2020-06-09 10:04 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 03/10] spi: dw: Add support for client driver memory operations Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:52 ` Mark Brown 2020-05-19 11:47 ` Lars Povlsen 2020-05-19 11:47 ` Lars Povlsen 2020-05-19 11:58 ` Mark Brown 2020-05-19 12:10 ` Lars Povlsen 2020-05-19 12:10 ` Lars Povlsen 2020-06-02 19:49 ` Serge Semin 2020-06-02 19:49 ` Serge Semin 2020-06-09 10:27 ` Lars Povlsen 2020-06-09 10:27 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 15:18 ` Mark Brown 2020-05-19 12:05 ` Lars Povlsen 2020-05-19 12:05 ` Lars Povlsen 2020-06-02 21:12 ` Serge Semin 2020-06-02 21:12 ` Serge Semin 2020-06-10 14:28 ` Lars Povlsen 2020-06-10 14:28 ` Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen [this message] 2020-05-13 14:00 ` [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Lars Povlsen 2020-05-13 15:25 ` Mark Brown 2020-06-02 23:07 ` Serge Semin 2020-06-02 23:07 ` Serge Semin 2020-06-10 12:27 ` Lars Povlsen 2020-06-10 12:27 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 07/10] " Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-14 10:25 ` Mark Brown 2020-05-19 9:29 ` Lars Povlsen 2020-05-19 9:29 ` Lars Povlsen 2020-06-02 23:22 ` Serge Semin 2020-06-02 23:22 ` Serge Semin 2020-05-13 14:00 ` [PATCH 08/10] arm64: dts: sparx5: Add SPI controller Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 09/10] arm64: dts: sparx5: Add spi-nor support Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 10/10] arm64: dts: sparx5: Add spi-nand devices Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-29 16:21 ` [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Serge Semin 2020-05-29 16:21 ` Serge Semin 2020-06-02 8:18 ` Lars Povlsen 2020-06-02 8:18 ` Lars Povlsen 2020-06-02 8:21 ` Serge Semin 2020-06-02 8:21 ` Serge Semin 2020-06-02 9:56 ` Mark Brown 2020-06-02 23:44 ` Serge Semin 2020-06-02 23:44 ` Serge Semin
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