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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org
Subject: [PULL v1 00/14] Xilinx queue 2020-05-14
Date: Thu, 14 May 2020 16:13:48 +0200	[thread overview]
Message-ID: <20200514141402.12498-1-edgar.iglesias@gmail.com> (raw)

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

The following changes since commit 035b448b84f3557206abc44d786c5d3db2638f7d:

  Merge remote-tracking branch 'remotes/gkurz/tags/9p-next-2020-05-14' into staging (2020-05-14 10:58:30 +0100)

are available in the Git repository at:

  git@github.com:edgarigl/qemu.git tags/edgar/xilinx-next-2020-05-14.for-upstream

for you to fetch changes up to 2ead1b18ca1bbc41c09a82d980e1e5f53afa08eb:

  target/microblaze: monitor: Increase the number of registers reported (2020-05-14 16:01:02 +0200)

----------------------------------------------------------------
Upstream

----------------------------------------------------------------
Edgar E. Iglesias (9):
      hw/net/xilinx_axienet: Auto-clear PHY Autoneg
      hw/net/xilinx_axienet: Cleanup stream->push assignment
      hw/net/xilinx_axienet: Remove unncessary cast
      hw/dma/xilinx_axidma: Add DMA memory-region property
      hw/core: stream: Add an end-of-packet flag
      hw/net/xilinx_axienet: Handle fragmented packets from DMA
      hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptor
      hw/dma/xilinx_axidma: s2mm: Support stream fragments
      MAINTAINERS: Add myself as streams maintainer

Joe Komlodi (4):
      target/microblaze: Fix FPU2 instruction check
      target/microblaze: gdb: Extend the number of registers presented to GDB
      target/microblaze: gdb: Fix incorrect SReg reporting
      target/microblaze: monitor: Increase the number of registers reported

Tong Ho (1):
      target/microblaze: Add MFS Rd,EDR translation

 include/hw/stream.h           |  5 ++-
 hw/core/stream.c              |  4 +-
 hw/dma/xilinx_axidma.c        | 75 ++++++++++++++++++++++-------------
 hw/net/xilinx_axienet.c       | 70 +++++++++++++++++++++++++--------
 hw/ssi/xilinx_spips.c         |  2 +-
 target/microblaze/cpu.c       |  2 +-
 target/microblaze/gdbstub.c   | 91 +++++++++++++++++++++++++++++++++++++++++--
 target/microblaze/translate.c | 19 +++++++--
 MAINTAINERS                   |  6 +++
 9 files changed, 218 insertions(+), 56 deletions(-)

-- 
2.20.1



             reply	other threads:[~2020-05-14 14:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-14 14:13 Edgar E. Iglesias [this message]
2020-05-14 14:13 ` [PULL v1 01/14] hw/net/xilinx_axienet: Auto-clear PHY Autoneg Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 02/14] hw/net/xilinx_axienet: Cleanup stream->push assignment Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 03/14] hw/net/xilinx_axienet: Remove unncessary cast Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 04/14] hw/dma/xilinx_axidma: Add DMA memory-region property Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 05/14] hw/core: stream: Add an end-of-packet flag Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 06/14] hw/net/xilinx_axienet: Handle fragmented packets from DMA Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 07/14] hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptor Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 08/14] hw/dma/xilinx_axidma: s2mm: Support stream fragments Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 09/14] MAINTAINERS: Add myself as streams maintainer Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 10/14] target/microblaze: Add MFS Rd,EDR translation Edgar E. Iglesias
2020-05-14 14:13 ` [PULL v1 11/14] target/microblaze: Fix FPU2 instruction check Edgar E. Iglesias
2020-05-14 14:14 ` [PULL v1 12/14] target/microblaze: gdb: Extend the number of registers presented to GDB Edgar E. Iglesias
2020-05-14 14:14 ` [PULL v1 13/14] target/microblaze: gdb: Fix incorrect SReg reporting Edgar E. Iglesias
2020-05-14 14:14 ` [PULL v1 14/14] target/microblaze: monitor: Increase the number of registers reported Edgar E. Iglesias
2020-05-14 15:17 ` [PULL v1 00/14] Xilinx queue 2020-05-14 Peter Maydell

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