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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: fernando.pacheco@intel.com, Matthew Auld <matthew.auld@intel.com>
Subject: [Intel-gfx] [PATCH 30/37] drm/i915/dg1: Update comp master/slave relationships for PHYs
Date: Wed, 20 May 2020 17:37:56 -0700	[thread overview]
Message-ID: <20200521003803.18936-31-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20200521003803.18936-1-lucas.demarchi@intel.com>

From: Matt Roper <matthew.d.roper@intel.com>

As with RKL, DG1's PHY C acts as a comp master for PHY D.

Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 8604d4392e6a..2fad4871d4e6 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	 *
 	 * ICL,TGL:
 	 *   A(master) -> B(slave), C(slave)
-	 * RKL:
+	 * RKL,DG1:
 	 *   A(master) -> B(slave)
 	 *   C(master) -> D(slave)
 	 *
 	 * We must set the IREFGEN bit for any PHY acting as a master
 	 * to another PHY.
 	 */
-	if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+	if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
 		return true;
 
 	return phy == PHY_A;
-- 
2.26.2

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  parent reply	other threads:[~2020-05-21  0:38 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-21  0:37 [Intel-gfx] [PATCH 00/37] Introduce DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 01/37] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 02/37] drm/i915/rkl: Add DDC pin mapping Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 03/37] drm/i915/rkl: Setup ports/phys Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 04/37] drm/i915/rkl: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 05/37] drm/i915/rkl: Handle HTI Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 06/37] drm/i915/rkl: Handle comp master/slave relationships for PHYs Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 07/37] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 08/37] drm/i915: make intel_{uncore, de}_rmw() more useful Lucas De Marchi
2020-05-21 17:24   ` Souza, Jose
2020-05-21 17:30     ` Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 09/37] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-05-26 18:10   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 10/37] drm/i915: add pcie snoop flag Lucas De Marchi
2020-05-21  8:15   ` Chris Wilson
2020-05-21  0:37 ` [Intel-gfx] [PATCH 11/37] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-05-26 17:34   ` Souza, Jose
2020-05-26 17:51     ` Lucas De Marchi
2020-05-26 18:02       ` Souza, Jose
2020-05-26 17:51   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 12/37] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-05-26 17:35   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 13/37] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 14/37] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 15/37] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 16/37] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 17/37] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 18/37] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-05-26 18:02   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 19/37] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 20/37] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 21/37] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 22/37] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 23/37] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 24/37] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 25/37] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 26/37] drm/i915/dg1: Handle GRF/IC ECC error irq Lucas De Marchi
2020-05-21  8:19   ` Chris Wilson
2020-05-21  0:37 ` [Intel-gfx] [PATCH 27/37] drm/i915/dg1: Log counter on SLM ECC error Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 28/37] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 29/37] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-05-21  0:37 ` Lucas De Marchi [this message]
2020-05-21  0:37 ` [Intel-gfx] [PATCH 31/37] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 32/37] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 33/37] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 34/37] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 35/37] drm/i915/dg1: Load DMC Lucas De Marchi
2020-05-26 17:42   ` Souza, Jose
2020-05-26 17:49     ` Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 36/37] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 37/37] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-05-26 17:44   ` Souza, Jose
2020-05-21  1:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-05-21  1:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-05-21  1:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-21 18:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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