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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers
Date: Tue, 26 May 2020 15:14:45 -0700	[thread overview]
Message-ID: <20200526221447.64110-4-jose.souza@intel.com> (raw)
In-Reply-To: <20200526221447.64110-1-jose.souza@intel.com>

This registers will be used to implement PSR2 software tracking.

BSpec: 55229
BSpec: 50424
BSpec: 50420
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++---
 1 file changed, 63 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9d50fe0f375..6f547e459d30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4566,6 +4566,18 @@ enum {
 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
 #define PSR2_SU_STATUS_FRAMES		8
 
+#define _PSR2_MAN_TRK_CTL_A				0x60910
+#define _PSR2_MAN_TRK_CTL_EDP				0x6f910
+#define PSR2_MAN_TRK_CTL(tran)				_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
+#define  PSR2_MAN_TRK_CTL_ENABLE			REG_BIT(31)
+#define  PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK	REG_GENMASK(30, 21)
+#define  PSR2_MAN_TRK_CTL_REGION_START_ADDR(val)	REG_FIELD_PREP(PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val)
+#define  PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK		REG_GENMASK(20, 11)
+#define  PSR2_MAN_TRK_CTL_REGION_END_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val)
+#define  PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME		REG_BIT(3)
+#define  PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME		REG_BIT(2)
+#define  PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE		REG_BIT(1)
+
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
@@ -7129,7 +7141,52 @@ enum {
 #define PLANE_COLOR_CTL(pipe, plane)	\
 	_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
 
-#/* SKL new cursor registers */
+#define _PLANE_SEL_FETCH_BASE_1_A		0x70890
+#define _PLANE_SEL_FETCH_BASE_2_A		0x708B0
+#define _PLANE_SEL_FETCH_BASE_3_A		0x708D0
+#define _PLANE_SEL_FETCH_BASE_4_A		0x708F0
+#define _PLANE_SEL_FETCH_BASE_5_A		0x70920
+#define _PLANE_SEL_FETCH_BASE_6_A		0x70940
+#define _PLANE_SEL_FETCH_BASE_7_A		0x70960
+#define _PLANE_SEL_FETCH_BASE_CUR_A		0x70880
+#define _PLANE_SEL_FETCH_BASE_1_B		0x70990
+
+#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \
+					     _PLANE_SEL_FETCH_BASE_1_A, \
+					     _PLANE_SEL_FETCH_BASE_2_A, \
+					     _PLANE_SEL_FETCH_BASE_3_A, \
+					     _PLANE_SEL_FETCH_BASE_4_A, \
+					     _PLANE_SEL_FETCH_BASE_5_A, \
+					     _PLANE_SEL_FETCH_BASE_6_A, \
+					     _PLANE_SEL_FETCH_BASE_7_A, \
+					     _PLANE_SEL_FETCH_BASE_CUR_A)
+#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A)
+#define PLANE_SEL_FETCH_BASE(pipe, plane) (_PLANE_SEL_FETCH_BASE_1(pipe) - \
+					   _PLANE_SEL_FETCH_BASE_1_A + \
+					   _PLANE_SEL_FETCH_BASE_A(plane))
+
+#define _PLANE_SEL_FETCH_CTL_1_A		0x70890
+#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \
+					       _PLANE_SEL_FETCH_CTL_1_A - \
+					       _PLANE_SEL_FETCH_BASE_1_A)
+#define PLANE_SET_FETCH_CTL_ENABLE		REG_BIT(31)
+
+#define _PLANE_SEL_FETCH_POS_1_A		0x70894
+#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \
+					       _PLANE_SEL_FETCH_POS_1_A - \
+					       _PLANE_SEL_FETCH_BASE_1_A)
+
+#define _PLANE_SEL_FETCH_SIZE_1_A		0x70898
+#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \
+						_PLANE_SEL_FETCH_SIZE_1_A - \
+						_PLANE_SEL_FETCH_BASE_1_A)
+
+#define _PLANE_SEL_FETCH_OFFSET_1_A		0x7089C
+#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \
+						  _PLANE_SEL_FETCH_OFFSET_1_A - \
+						  _PLANE_SEL_FETCH_BASE_1_A)
+
+/* SKL new cursor registers */
 #define _CUR_BUF_CFG_A				0x7017c
 #define _CUR_BUF_CFG_B				0x7117c
 #define CUR_BUF_CFG(pipe)	_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
@@ -7775,11 +7832,12 @@ enum {
 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
 
-#define CHICKEN_PAR1_1		_MMIO(0x42080)
+#define CHICKEN_PAR1_1			_MMIO(0x42080)
 #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
-#define  DPA_MASK_VBLANK_SRD	(1 << 15)
-#define  FORCE_ARB_IDLE_PLANES	(1 << 14)
-#define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)
+#define  DPA_MASK_VBLANK_SRD		(1 << 15)
+#define  FORCE_ARB_IDLE_PLANES		(1 << 14)
+#define  SKL_EDP_PSR_FIX_RDWRAP		(1 << 3)
+#define  IGNORE_PSR2_HW_TRACKING	(1 << 1)
 
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
-- 
2.26.2

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  parent reply	other threads:[~2020-05-26 22:12 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-26 22:14 [Intel-gfx] [PATCH 1/6] drm/i915/rkl: Disable PSR2 José Roberto de Souza
2020-05-26 22:14 ` [Intel-gfx] [PATCH 2/6] drm/i915: Add plane damage clips property José Roberto de Souza
2020-06-12 15:15   ` Mun, Gwan-gyeong
2020-06-12 15:25   ` Ville Syrjälä
2020-06-12 15:30     ` Souza, Jose
2020-06-12 15:37       ` Ville Syrjälä
2020-06-12 15:42         ` Souza, Jose
2020-05-26 22:14 ` [Intel-gfx] [PATCH 3/6] drm/i915: Reorder intel_psr2_config_valid() José Roberto de Souza
2020-06-12 15:42   ` Mun, Gwan-gyeong
2020-05-26 22:14 ` José Roberto de Souza [this message]
2020-06-12 20:57   ` [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers Mun, Gwan-gyeong
2020-06-12 21:18     ` Souza, Jose
2020-06-12 21:49       ` Mun, Gwan-gyeong
2020-06-15 18:37         ` Mun, Gwan-gyeong
2020-06-15 19:23           ` Souza, Jose
2020-06-25 21:41             ` Souza, Jose
2020-05-26 22:14 ` [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch José Roberto de Souza
2020-06-12 16:30   ` Ville Syrjälä
2020-06-12 20:33     ` Souza, Jose
2020-06-15 16:40       ` Ville Syrjälä
2020-06-16 15:16         ` Mun, Gwan-gyeong
2020-06-16 17:29           ` Souza, Jose
2020-06-16 20:33             ` Mun, Gwan-gyeong
2020-06-16 21:00               ` Souza, Jose
2020-05-26 22:14 ` [Intel-gfx] [PATCH 6/6] drm/i915: Implement PSR2 selective fetch WAs José Roberto de Souza
2020-05-26 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/rkl: Disable PSR2 Patchwork
2020-05-26 22:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-27  1:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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