From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 01/11] drm/i915/gt: Start timeslice on partial submission
Date: Thu, 28 May 2020 22:15:14 +0100 [thread overview]
Message-ID: <20200528211524.29107-1-chris@chris-wilson.co.uk> (raw)
We may choose to only submit ELSP[0], even though we have sufficient
requests to fill the whole ELSP. Normally, we only start timeslicing if
we fill more than one port, but in this case we need to start
timeslicing for the queue that we choose not to submit.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 69fff36ec0cc..6fc0966b75ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2358,8 +2358,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
if (last->context == rq->context)
goto done;
- if (i915_request_has_sentinel(last))
+ if (i915_request_has_sentinel(last)) {
+ start_timeslice(engine, rq_prio(rq));
goto done;
+ }
/*
* If GVT overrides us we only ever submit
--
2.20.1
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next reply other threads:[~2020-05-28 21:15 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 21:15 Chris Wilson [this message]
2020-05-28 21:15 ` [Intel-gfx] [PATCH 02/11] drm/i915/gem: Mark the buffer pool as active for the cmdparser Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 03/11] drm/i915/gem: Async GPU relocations only Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 04/11] drm/i915: Add list_for_each_entry_safe_continue_reverse Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 05/11] drm/i915/gem: Separate reloc validation into an earlier step Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 06/11] drm/i915/gem: Lift GPU relocation allocation Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 07/11] drm/i915/gem: Build the reloc request first Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 08/11] drm/i915/gem: Add all GPU reloc awaits/signals en masse Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 09/11] dma-buf: Proxy fence, an unsignaled fence placeholder Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 10/11] drm/i915: Unpeel awaits on a proxy fence Chris Wilson
2020-05-28 21:15 ` [Intel-gfx] [PATCH 11/11] drm/i915/gem: Make relocations atomic within execbuf Chris Wilson
2020-05-28 22:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/11] drm/i915/gt: Start timeslice on partial submission Patchwork
2020-05-28 22:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-05-28 23:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-29 2:42 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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