From: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Jonathan Hunter
<jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Georgi Djakov
<georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
MyungJoo Ham
<myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
Kyungmin Park
<kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
Mikko Perttunen <cyndis-/1wQRMveznE@public.gmane.org>
Cc: "Artur Świgoń" <a.swigon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v3 24/39] dt-bindings: memory: tegra30: Add memory client IDs
Date: Sun, 7 Jun 2020 21:55:15 +0300 [thread overview]
Message-ID: <20200607185530.18113-25-digetx@gmail.com> (raw)
In-Reply-To: <20200607185530.18113-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Each memory client have a unique hardware ID, this patch adds these IDs.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
index 169f005fbc78..930f708aca17 100644
--- a/include/dt-bindings/memory/tegra30-mc.h
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -41,4 +41,71 @@
#define TEGRA30_MC_RESET_VDE 16
#define TEGRA30_MC_RESET_VI 17
+#define TEGRA30_MC_PTCR 0
+#define TEGRA30_MC_DISPLAY0A 1
+#define TEGRA30_MC_DISPLAY0AB 2
+#define TEGRA30_MC_DISPLAY0B 3
+#define TEGRA30_MC_DISPLAY0BB 4
+#define TEGRA30_MC_DISPLAY0C 5
+#define TEGRA30_MC_DISPLAY0CB 6
+#define TEGRA30_MC_DISPLAY1B 7
+#define TEGRA30_MC_DISPLAY1BB 8
+#define TEGRA30_MC_EPPUP 9
+#define TEGRA30_MC_G2PR 10
+#define TEGRA30_MC_G2SR 11
+#define TEGRA30_MC_MPEUNIFBR 12
+#define TEGRA30_MC_VIRUV 13
+#define TEGRA30_MC_AFIR 14
+#define TEGRA30_MC_AVPCARM7R 15
+#define TEGRA30_MC_DISPLAYHC 16
+#define TEGRA30_MC_DISPLAYHCB 17
+#define TEGRA30_MC_FDCDRD 18
+#define TEGRA30_MC_FDCDRD2 19
+#define TEGRA30_MC_G2DR 20
+#define TEGRA30_MC_HDAR 21
+#define TEGRA30_MC_HOST1XDMAR 22
+#define TEGRA30_MC_HOST1XR 23
+#define TEGRA30_MC_IDXSRD 24
+#define TEGRA30_MC_IDXSRD2 25
+#define TEGRA30_MC_MPE_IPRED 26
+#define TEGRA30_MC_MPEAMEMRD 27
+#define TEGRA30_MC_MPECSRD 28
+#define TEGRA30_MC_PPCSAHBDMAR 29
+#define TEGRA30_MC_PPCSAHBSLVR 30
+#define TEGRA30_MC_SATAR 31
+#define TEGRA30_MC_TEXSRD 32
+#define TEGRA30_MC_TEXSRD2 33
+#define TEGRA30_MC_VDEBSEVR 34
+#define TEGRA30_MC_VDEMBER 35
+#define TEGRA30_MC_VDEMCER 36
+#define TEGRA30_MC_VDETPER 37
+#define TEGRA30_MC_MPCORELPR 38
+#define TEGRA30_MC_MPCORER 39
+#define TEGRA30_MC_EPPU 40
+#define TEGRA30_MC_EPPV 41
+#define TEGRA30_MC_EPPY 42
+#define TEGRA30_MC_MPEUNIFBW 43
+#define TEGRA30_MC_VIWSB 44
+#define TEGRA30_MC_VIWU 45
+#define TEGRA30_MC_VIWV 46
+#define TEGRA30_MC_VIWY 47
+#define TEGRA30_MC_G2DW 48
+#define TEGRA30_MC_AFIW 49
+#define TEGRA30_MC_AVPCARM7W 50
+#define TEGRA30_MC_FDCDWR 51
+#define TEGRA30_MC_FDCDWR2 52
+#define TEGRA30_MC_HDAW 53
+#define TEGRA30_MC_HOST1XW 54
+#define TEGRA30_MC_ISPW 55
+#define TEGRA30_MC_MPCORELPW 56
+#define TEGRA30_MC_MPCOREW 57
+#define TEGRA30_MC_MPECSWR 58
+#define TEGRA30_MC_PPCSAHBDMAW 59
+#define TEGRA30_MC_PPCSAHBSLVW 60
+#define TEGRA30_MC_SATAW 61
+#define TEGRA30_MC_VDEBSEVW 62
+#define TEGRA30_MC_VDEDBGW 63
+#define TEGRA30_MC_VDEMBEW 64
+#define TEGRA30_MC_VDETPMW 65
+
#endif
--
2.26.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Georgi Djakov <georgi.djakov@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
MyungJoo Ham <myungjoo.ham@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Mikko Perttunen <cyndis@kapsi.fi>
Cc: "Artur Świgoń" <a.swigon@samsung.com>,
linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org
Subject: [PATCH v3 24/39] dt-bindings: memory: tegra30: Add memory client IDs
Date: Sun, 7 Jun 2020 21:55:15 +0300 [thread overview]
Message-ID: <20200607185530.18113-25-digetx@gmail.com> (raw)
In-Reply-To: <20200607185530.18113-1-digetx@gmail.com>
Each memory client have a unique hardware ID, this patch adds these IDs.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
index 169f005fbc78..930f708aca17 100644
--- a/include/dt-bindings/memory/tegra30-mc.h
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -41,4 +41,71 @@
#define TEGRA30_MC_RESET_VDE 16
#define TEGRA30_MC_RESET_VI 17
+#define TEGRA30_MC_PTCR 0
+#define TEGRA30_MC_DISPLAY0A 1
+#define TEGRA30_MC_DISPLAY0AB 2
+#define TEGRA30_MC_DISPLAY0B 3
+#define TEGRA30_MC_DISPLAY0BB 4
+#define TEGRA30_MC_DISPLAY0C 5
+#define TEGRA30_MC_DISPLAY0CB 6
+#define TEGRA30_MC_DISPLAY1B 7
+#define TEGRA30_MC_DISPLAY1BB 8
+#define TEGRA30_MC_EPPUP 9
+#define TEGRA30_MC_G2PR 10
+#define TEGRA30_MC_G2SR 11
+#define TEGRA30_MC_MPEUNIFBR 12
+#define TEGRA30_MC_VIRUV 13
+#define TEGRA30_MC_AFIR 14
+#define TEGRA30_MC_AVPCARM7R 15
+#define TEGRA30_MC_DISPLAYHC 16
+#define TEGRA30_MC_DISPLAYHCB 17
+#define TEGRA30_MC_FDCDRD 18
+#define TEGRA30_MC_FDCDRD2 19
+#define TEGRA30_MC_G2DR 20
+#define TEGRA30_MC_HDAR 21
+#define TEGRA30_MC_HOST1XDMAR 22
+#define TEGRA30_MC_HOST1XR 23
+#define TEGRA30_MC_IDXSRD 24
+#define TEGRA30_MC_IDXSRD2 25
+#define TEGRA30_MC_MPE_IPRED 26
+#define TEGRA30_MC_MPEAMEMRD 27
+#define TEGRA30_MC_MPECSRD 28
+#define TEGRA30_MC_PPCSAHBDMAR 29
+#define TEGRA30_MC_PPCSAHBSLVR 30
+#define TEGRA30_MC_SATAR 31
+#define TEGRA30_MC_TEXSRD 32
+#define TEGRA30_MC_TEXSRD2 33
+#define TEGRA30_MC_VDEBSEVR 34
+#define TEGRA30_MC_VDEMBER 35
+#define TEGRA30_MC_VDEMCER 36
+#define TEGRA30_MC_VDETPER 37
+#define TEGRA30_MC_MPCORELPR 38
+#define TEGRA30_MC_MPCORER 39
+#define TEGRA30_MC_EPPU 40
+#define TEGRA30_MC_EPPV 41
+#define TEGRA30_MC_EPPY 42
+#define TEGRA30_MC_MPEUNIFBW 43
+#define TEGRA30_MC_VIWSB 44
+#define TEGRA30_MC_VIWU 45
+#define TEGRA30_MC_VIWV 46
+#define TEGRA30_MC_VIWY 47
+#define TEGRA30_MC_G2DW 48
+#define TEGRA30_MC_AFIW 49
+#define TEGRA30_MC_AVPCARM7W 50
+#define TEGRA30_MC_FDCDWR 51
+#define TEGRA30_MC_FDCDWR2 52
+#define TEGRA30_MC_HDAW 53
+#define TEGRA30_MC_HOST1XW 54
+#define TEGRA30_MC_ISPW 55
+#define TEGRA30_MC_MPCORELPW 56
+#define TEGRA30_MC_MPCOREW 57
+#define TEGRA30_MC_MPECSWR 58
+#define TEGRA30_MC_PPCSAHBDMAW 59
+#define TEGRA30_MC_PPCSAHBSLVW 60
+#define TEGRA30_MC_SATAW 61
+#define TEGRA30_MC_VDEBSEVW 62
+#define TEGRA30_MC_VDEDBGW 63
+#define TEGRA30_MC_VDEMBEW 64
+#define TEGRA30_MC_VDETPMW 65
+
#endif
--
2.26.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Georgi Djakov <georgi.djakov@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
MyungJoo Ham <myungjoo.ham@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Mikko Perttunen <cyndis@kapsi.fi>
Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
"Artur Świgoń" <a.swigon@samsung.com>,
linux-tegra@vger.kernel.org
Subject: [PATCH v3 24/39] dt-bindings: memory: tegra30: Add memory client IDs
Date: Sun, 7 Jun 2020 21:55:15 +0300 [thread overview]
Message-ID: <20200607185530.18113-25-digetx@gmail.com> (raw)
In-Reply-To: <20200607185530.18113-1-digetx@gmail.com>
Each memory client have a unique hardware ID, this patch adds these IDs.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
index 169f005fbc78..930f708aca17 100644
--- a/include/dt-bindings/memory/tegra30-mc.h
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -41,4 +41,71 @@
#define TEGRA30_MC_RESET_VDE 16
#define TEGRA30_MC_RESET_VI 17
+#define TEGRA30_MC_PTCR 0
+#define TEGRA30_MC_DISPLAY0A 1
+#define TEGRA30_MC_DISPLAY0AB 2
+#define TEGRA30_MC_DISPLAY0B 3
+#define TEGRA30_MC_DISPLAY0BB 4
+#define TEGRA30_MC_DISPLAY0C 5
+#define TEGRA30_MC_DISPLAY0CB 6
+#define TEGRA30_MC_DISPLAY1B 7
+#define TEGRA30_MC_DISPLAY1BB 8
+#define TEGRA30_MC_EPPUP 9
+#define TEGRA30_MC_G2PR 10
+#define TEGRA30_MC_G2SR 11
+#define TEGRA30_MC_MPEUNIFBR 12
+#define TEGRA30_MC_VIRUV 13
+#define TEGRA30_MC_AFIR 14
+#define TEGRA30_MC_AVPCARM7R 15
+#define TEGRA30_MC_DISPLAYHC 16
+#define TEGRA30_MC_DISPLAYHCB 17
+#define TEGRA30_MC_FDCDRD 18
+#define TEGRA30_MC_FDCDRD2 19
+#define TEGRA30_MC_G2DR 20
+#define TEGRA30_MC_HDAR 21
+#define TEGRA30_MC_HOST1XDMAR 22
+#define TEGRA30_MC_HOST1XR 23
+#define TEGRA30_MC_IDXSRD 24
+#define TEGRA30_MC_IDXSRD2 25
+#define TEGRA30_MC_MPE_IPRED 26
+#define TEGRA30_MC_MPEAMEMRD 27
+#define TEGRA30_MC_MPECSRD 28
+#define TEGRA30_MC_PPCSAHBDMAR 29
+#define TEGRA30_MC_PPCSAHBSLVR 30
+#define TEGRA30_MC_SATAR 31
+#define TEGRA30_MC_TEXSRD 32
+#define TEGRA30_MC_TEXSRD2 33
+#define TEGRA30_MC_VDEBSEVR 34
+#define TEGRA30_MC_VDEMBER 35
+#define TEGRA30_MC_VDEMCER 36
+#define TEGRA30_MC_VDETPER 37
+#define TEGRA30_MC_MPCORELPR 38
+#define TEGRA30_MC_MPCORER 39
+#define TEGRA30_MC_EPPU 40
+#define TEGRA30_MC_EPPV 41
+#define TEGRA30_MC_EPPY 42
+#define TEGRA30_MC_MPEUNIFBW 43
+#define TEGRA30_MC_VIWSB 44
+#define TEGRA30_MC_VIWU 45
+#define TEGRA30_MC_VIWV 46
+#define TEGRA30_MC_VIWY 47
+#define TEGRA30_MC_G2DW 48
+#define TEGRA30_MC_AFIW 49
+#define TEGRA30_MC_AVPCARM7W 50
+#define TEGRA30_MC_FDCDWR 51
+#define TEGRA30_MC_FDCDWR2 52
+#define TEGRA30_MC_HDAW 53
+#define TEGRA30_MC_HOST1XW 54
+#define TEGRA30_MC_ISPW 55
+#define TEGRA30_MC_MPCORELPW 56
+#define TEGRA30_MC_MPCOREW 57
+#define TEGRA30_MC_MPECSWR 58
+#define TEGRA30_MC_PPCSAHBDMAW 59
+#define TEGRA30_MC_PPCSAHBSLVW 60
+#define TEGRA30_MC_SATAW 61
+#define TEGRA30_MC_VDEBSEVW 62
+#define TEGRA30_MC_VDEDBGW 63
+#define TEGRA30_MC_VDEMBEW 64
+#define TEGRA30_MC_VDETPMW 65
+
#endif
--
2.26.0
_______________________________________________
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dri-devel@lists.freedesktop.org
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next prev parent reply other threads:[~2020-06-07 18:55 UTC|newest]
Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-07 18:54 [PATCH v3 00/39] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` [PATCH v3 02/39] clk: tegra: Remove Memory Controller lock Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 12/39] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 13/39] PM / devfreq: tegra30: " Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 17/39] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 19/39] dt-bindings: memory: tegra20: emc: Document new interconnect property Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 22/39] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 30/39] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 33/39] memory: tegra30-emc: " Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 34/39] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
[not found] ` <20200607185530.18113-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-06-07 18:54 ` [PATCH v3 01/39] clk: Export clk_hw_reparent() Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` [PATCH v3 03/39] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` [PATCH v3 04/39] memory: tegra20-emc: Make driver modular Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` [PATCH v3 05/39] memory: tegra30-emc: " Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` [PATCH v3 06/39] memory: tegra124-emc: " Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` [PATCH v3 07/39] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` [PATCH v3 08/39] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:54 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 09/39] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 10/39] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 11/39] PM / devfreq: tegra30: " Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 14/39] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 15/39] PM / devfreq: tegra30: " Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 16/39] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 18/39] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 20/39] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 21/39] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 23/39] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
[not found] ` <20200607185530.18113-24-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-06-09 20:01 ` Rob Herring
2020-06-09 20:01 ` Rob Herring
2020-06-09 20:01 ` Rob Herring
2020-06-07 18:55 ` Dmitry Osipenko [this message]
2020-06-07 18:55 ` [PATCH v3 24/39] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
[not found] ` <20200607185530.18113-25-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-06-09 20:02 ` Rob Herring
2020-06-09 20:02 ` Rob Herring
2020-06-09 20:02 ` Rob Herring
2020-06-07 18:55 ` [PATCH v3 25/39] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 26/39] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 27/39] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 28/39] memory: tegra: Register as interconnect provider Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 23:06 ` kernel test robot
2020-06-07 23:38 ` kernel test robot
2020-06-08 0:13 ` kernel test robot
2020-06-07 18:55 ` [PATCH v3 29/39] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 31/39] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
[not found] ` <20200607185530.18113-32-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-06-07 21:47 ` Dmitry Osipenko
2020-06-07 21:47 ` Dmitry Osipenko
2020-06-07 21:47 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 32/39] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 35/39] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 36/39] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 37/39] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 39/39] ARM: multi_v7_defconfig: Enable interconnect API Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
2020-06-07 18:55 ` [PATCH v3 38/39] ARM: tegra: Enable interconnect API in tegra_defconfig Dmitry Osipenko
2020-06-07 18:55 ` Dmitry Osipenko
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