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From: Eric Auger <eric.auger@redhat.com>
To: eric.auger.pro@gmail.com, eric.auger@redhat.com,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	peter.maydell@linaro.org, peterx@redhat.com
Cc: jean-philippe@linaro.org, robh@kernel.org, robin.murphy@arm.com,
	mst@redhat.com, zhangfei.gao@foxmail.com,
	shameerali.kolothum.thodi@huawei.com, will@kernel.org
Subject: [PATCH RESEND 9/9] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
Date: Thu, 11 Jun 2020 18:15:00 +0200	[thread overview]
Message-ID: <20200611161500.23580-10-eric.auger@redhat.com> (raw)
In-Reply-To: <20200611161500.23580-1-eric.auger@redhat.com>

Expose the RIL bit so that the guest driver uses range
invalidation.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
 hw/arm/smmuv3-internal.h | 1 +
 hw/arm/smmuv3.c          | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 5babf72f7d..4e7ec252ed 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -54,6 +54,7 @@ REG32(IDR1,                0x4)
 
 REG32(IDR2,                0x8)
 REG32(IDR3,                0xc)
+    FIELD(IDR3, RIL,          10, 1);
 REG32(IDR4,                0x10)
 REG32(IDR5,                0x14)
      FIELD(IDR5, OAS,         0, 3);
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 4dff438809..78920f5158 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -254,6 +254,8 @@ static void smmuv3_init_regs(SMMUv3State *s)
     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS,   SMMU_CMDQS);
 
+    s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
+
    /* 4K and 64K granule support */
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
-- 
2.20.1



  parent reply	other threads:[~2020-06-11 16:35 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-11 16:14 [PATCH RESEND 0/9] SMMUv3.2 Range-based TLB Invalidation Support Eric Auger
2020-06-11 16:14 ` [PATCH RESEND 1/9] hw/arm/smmu-common: Factorize some code in smmu_ptw_64() Eric Auger
2020-06-25 14:49   ` Peter Maydell
2020-06-26 13:53     ` Auger Eric
2020-06-11 16:14 ` [PATCH RESEND 2/9] hw/arm/smmu-common: Add IOTLB helpers Eric Auger
2020-06-25 14:54   ` Peter Maydell
2020-06-11 16:14 ` [PATCH RESEND 3/9] hw/arm/smmu: Simplify the IOTLB key format Eric Auger
2020-06-25 15:03   ` Peter Maydell
2020-06-26 13:53     ` Auger Eric
2020-06-11 16:14 ` [PATCH RESEND 4/9] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value Eric Auger
2020-06-25 15:13   ` Peter Maydell
2020-06-11 16:14 ` [PATCH RESEND 5/9] hw/arm/smmuv3: Store the starting level in SMMUTransTableInfo Eric Auger
2020-06-25 15:15   ` Peter Maydell
2020-06-26 13:58     ` Auger Eric
2020-06-11 16:14 ` [PATCH RESEND 6/9] hw/arm/smmu-common: Manage IOTLB block entries Eric Auger
2020-06-25 15:30   ` Peter Maydell
2020-06-26 13:53     ` Auger Eric
2020-06-30 15:46       ` Auger Eric
2020-06-30 15:50       ` Peter Maydell
2020-06-30 16:29         ` Auger Eric
2020-07-02 14:39           ` Auger Eric
2020-06-11 16:14 ` [PATCH RESEND 7/9] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper Eric Auger
2020-06-25 15:34   ` Peter Maydell
2020-06-11 16:14 ` [PATCH RESEND 8/9] hw/arm/smmuv3: Get prepared for range invalidation Eric Auger
2020-06-25 15:43   ` Peter Maydell
2020-06-11 16:15 ` Eric Auger [this message]
2020-06-25 15:40   ` [PATCH RESEND 9/9] hw/arm/smmuv3: Advertise SMMUv3.2 " Peter Maydell

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