From: Lars Povlsen <lars.povlsen@microchip.com> To: SoC Team <soc@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Stephen Boyd <sboyd@kernel.org>, Linus Walleij <linus.walleij@linaro.org> Cc: Lars Povlsen <lars.povlsen@microchip.com>, Steen Hegelund <Steen.Hegelund@microchip.com>, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, Olof Johansson <olof@lixom.net>, "Michael Turquette" <mturquette@baylibre.com>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Alexandre Belloni <alexandre.belloni@bootlin.com> Subject: [PATCH v3 03/10] arm64: dts: sparx5: Add basic cpu support Date: Mon, 15 Jun 2020 15:32:35 +0200 [thread overview] Message-ID: <20200615133242.24911-4-lars.povlsen@microchip.com> (raw) In-Reply-To: <20200615133242.24911-1-lars.povlsen@microchip.com> This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option). Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/microchip/Makefile | 4 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 142 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb134.dts | 17 +++ .../dts/microchip/sparx5_pcb134_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb135.dts | 17 +++ .../dts/microchip/sparx5_pcb135_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++ 12 files changed, 268 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/Makefile create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 13553b77ed4f7..20056e369e9e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2117,6 +2117,7 @@ M: Steen Hegelund <Steen.Hegelund@microchip.com> M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported +F: arch/arm64/boot/dts/microchip/ N: sparx5 ARM/MIOA701 MACHINE SUPPORT diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f19b762c008d8..9680a7f20c307 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -17,6 +17,7 @@ subdir-y += intel subdir-y += lg subdir-y += marvell subdir-y += mediatek +subdir-y += microchip subdir-y += nvidia subdir-y += qcom subdir-y += realtek diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile new file mode 100644 index 0000000000000..c6e0313eea0f9 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi new file mode 100644 index 0000000000000..4a54b7d039167 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "microchip,sparx5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + clocks: clocks { + #address-cells = <2>; + #size-cells = <1>; + ranges; + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; + }; + }; + + axi: axi@600000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@600300000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ + <0x6 0x00340000 0xc0000>, /* GICR */ + <0x6 0x00200000 0x2000>, /* GICC */ + <0x6 0x00210000 0x2000>, /* GICV */ + <0x6 0x00220000 0x2000>; /* GICH */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart0: serial@600100000 { + compatible = "ns16550a"; + reg = <0x6 0x00100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart1: serial@600102000 { + compatible = "ns16550a"; + reg = <0x6 0x00102000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + timer1: timer@600105000 { + compatible = "snps,dw-apb-timer"; + reg = <0x6 0x00105000 0x1000>; + clocks = <&ahb_clk>; + clock-names = "timer"; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts new file mode 100644 index 0000000000000..d7f985f7ee020 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/ { + model = "Sparx5 PCB125 Reference Board"; + compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts new file mode 100644 index 0000000000000..feee4e99ff57c --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi new file mode 100644 index 0000000000000..005cf6babb9b3 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts new file mode 100644 index 0000000000000..10081a66961bb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts new file mode 100644 index 0000000000000..20e409a9be196 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi new file mode 100644 index 0000000000000..005cf6babb9b3 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts new file mode 100644 index 0000000000000..741f0e12260e5 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi new file mode 100644 index 0000000000000..1f99d0db1284f --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5.dtsi" + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Lars Povlsen <lars.povlsen@microchip.com> To: SoC Team <soc@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Stephen Boyd <sboyd@kernel.org>, Linus Walleij <linus.walleij@linaro.org> Cc: devicetree@vger.kernel.org, Alexandre Belloni <alexandre.belloni@bootlin.com>, Steen Hegelund <Steen.Hegelund@microchip.com>, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Olof Johansson <olof@lixom.net>, Michael Turquette <mturquette@baylibre.com>, Lars Povlsen <lars.povlsen@microchip.com> Subject: [PATCH v3 03/10] arm64: dts: sparx5: Add basic cpu support Date: Mon, 15 Jun 2020 15:32:35 +0200 [thread overview] Message-ID: <20200615133242.24911-4-lars.povlsen@microchip.com> (raw) In-Reply-To: <20200615133242.24911-1-lars.povlsen@microchip.com> This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option). Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/microchip/Makefile | 4 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 142 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb134.dts | 17 +++ .../dts/microchip/sparx5_pcb134_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb135.dts | 17 +++ .../dts/microchip/sparx5_pcb135_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++ 12 files changed, 268 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/Makefile create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 13553b77ed4f7..20056e369e9e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2117,6 +2117,7 @@ M: Steen Hegelund <Steen.Hegelund@microchip.com> M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported +F: arch/arm64/boot/dts/microchip/ N: sparx5 ARM/MIOA701 MACHINE SUPPORT diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f19b762c008d8..9680a7f20c307 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -17,6 +17,7 @@ subdir-y += intel subdir-y += lg subdir-y += marvell subdir-y += mediatek +subdir-y += microchip subdir-y += nvidia subdir-y += qcom subdir-y += realtek diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile new file mode 100644 index 0000000000000..c6e0313eea0f9 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi new file mode 100644 index 0000000000000..4a54b7d039167 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "microchip,sparx5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + clocks: clocks { + #address-cells = <2>; + #size-cells = <1>; + ranges; + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; + }; + }; + + axi: axi@600000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@600300000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ + <0x6 0x00340000 0xc0000>, /* GICR */ + <0x6 0x00200000 0x2000>, /* GICC */ + <0x6 0x00210000 0x2000>, /* GICV */ + <0x6 0x00220000 0x2000>; /* GICH */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart0: serial@600100000 { + compatible = "ns16550a"; + reg = <0x6 0x00100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart1: serial@600102000 { + compatible = "ns16550a"; + reg = <0x6 0x00102000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + timer1: timer@600105000 { + compatible = "snps,dw-apb-timer"; + reg = <0x6 0x00105000 0x1000>; + clocks = <&ahb_clk>; + clock-names = "timer"; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts new file mode 100644 index 0000000000000..d7f985f7ee020 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/ { + model = "Sparx5 PCB125 Reference Board"; + compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts new file mode 100644 index 0000000000000..feee4e99ff57c --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi new file mode 100644 index 0000000000000..005cf6babb9b3 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts new file mode 100644 index 0000000000000..10081a66961bb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts new file mode 100644 index 0000000000000..20e409a9be196 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi new file mode 100644 index 0000000000000..005cf6babb9b3 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts new file mode 100644 index 0000000000000..741f0e12260e5 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi new file mode 100644 index 0000000000000..1f99d0db1284f --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5.dtsi" + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-15 13:34 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-15 13:32 [PATCH v3 00/10] Adding support for Microchip Sparx5 SoC Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-06-15 13:32 ` [PATCH v3 01/10] dt-bindings: arm: sparx5: Add documentation " Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-07-13 18:40 ` Rob Herring 2020-07-13 18:40 ` Rob Herring 2020-06-15 13:32 ` [PATCH v3 02/10] arm64: sparx5: Add support for Microchip 2xA53 SoC Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen [this message] 2020-06-15 13:32 ` [PATCH v3 03/10] arm64: dts: sparx5: Add basic cpu support Lars Povlsen 2020-06-15 13:32 ` [PATCH v3 04/10] arm64: dts: sparx5: Add pinctrl support Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-06-15 13:32 ` [PATCH v3 05/10] pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-06-20 21:10 ` Linus Walleij 2020-06-20 21:10 ` Linus Walleij 2020-06-22 7:54 ` Lars Povlsen 2020-07-07 11:58 ` Linus Walleij 2020-07-07 11:58 ` Linus Walleij 2020-06-15 13:32 ` [PATCH v3 06/10] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-07-13 18:41 ` Rob Herring 2020-07-13 18:41 ` Rob Herring 2020-06-15 13:32 ` [PATCH v3 07/10] dt-bindings: clock: sparx5: Add bindings include file Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-07-13 18:41 ` Rob Herring 2020-07-13 18:41 ` Rob Herring 2020-06-15 13:32 ` [PATCH v3 08/10] clk: sparx5: Add Sparx5 SoC DPLL clock driver Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-07-24 8:41 ` Stephen Boyd 2020-07-24 12:19 ` Lars Povlsen 2020-07-24 12:19 ` Lars Povlsen 2020-06-15 13:32 ` [PATCH v3 09/10] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-06-15 13:32 ` [PATCH v3 10/10] arm64: dts: sparx5: Add i2c devices, i2c muxes Lars Povlsen 2020-06-15 13:32 ` Lars Povlsen 2020-07-22 20:32 ` [PATCH v3 00/10] Adding support for Microchip Sparx5 SoC Arnd Bergmann 2020-07-22 20:32 ` Arnd Bergmann 2020-07-23 10:09 ` Lars Povlsen 2020-07-23 10:09 ` Lars Povlsen
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