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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 00/32] Introduce DG1
Date: Wed, 17 Jun 2020 17:42:08 -0700	[thread overview]
Message-ID: <20200618004240.16263-1-lucas.demarchi@intel.com> (raw)

v2:
- Remove some wrong/unneeded patches
- Collect R-b
- Rebase

As in previous version, the RKL patches are here only for completeness
and avoid future conflicts, not to be reviewed/applied.

Original cover:
DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.

While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it could be useful to return the
previous value. The patch for that is included here, but I ended up
not using and it can be dropped if there is no interest.

Abdiel Janulgue (2):
  drm/i915/dg1: add initial DG-1 definitions
  drm/i915/dg1: Add DG1 PCI IDs

Aditya Swarup (4):
  drm/i915/dg1: Add DPLL macros for DG1
  drm/i915/dg1: Add and setup DPLLs for DG1
  drm/i915/dg1: Enable DPLL for DG1
  drm/i915/dg1: Enable first 2 ports for DG1

Anshuman Gupta (1):
  drm/i915/dg1: DG1 does not support DC6

Anusha Srivatsa (1):
  drm/i915/dg1: Remove SHPD_FILTER_CNT register programming

Clinton A Taylor (1):
  drm/i915/dg1: invert HPD pins

Lucas De Marchi (7):
  drm/i915/dg1: add support for the master unit interrupt
  drm/i915/dg1: Add fake PCH
  drm/i915/dg1: Define MOCS table for DG1
  drm/i915/dg1: add hpd interrupt handling
  drm/i915/dg1: gmbus pin mapping
  drm/i915/dg1: map/unmap pll clocks
  drm/i915/dg1: enable PORT C/D aka D/E

Matt Atwood (1):
  drm/i915/dg1: Load DMC

Matt Roper (11):
  drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
  drm/i915/rkl: Add DPLL4 support
  drm/i915/rkl: Handle HTI
  drm/i915/rkl: Add initial workarounds
  drm/i915/rkl: Add Wa_14011224835 for PHY B initialization
  drm/i915/dg1: Initialize RAWCLK properly
  drm/i915/dg1: Wait for pcode/uncore handshake at startup
  drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
  drm/i915/dg1: Update comp master/slave relationships for PHYs
  drm/i915/dg1: Update voltage swing tables for DP
  drm/i915/dg1: provide port/phy mapping for vbt

Stuart Summers (2):
  drm/i915: Add has_master_unit_irq flag
  drm/i915/dg1: Add initial DG1 workarounds

Uma Shankar (1):
  drm/i915/dg1: Add DG1 power wells

Venkata Sandeep Dhanalakota (1):
  drm/i915/dg1: Increase mmio size to 4MB

 drivers/gpu/drm/i915/display/intel_bios.c     |  12 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  16 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    |  33 ++-
 drivers/gpu/drm/i915/display/intel_csr.c      |  19 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 144 +++++++++++-
 drivers/gpu/drm/i915/display/intel_display.c  |  87 +++++++-
 .../drm/i915/display/intel_display_power.c    | 211 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 117 ++++++++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  32 ++-
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  15 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   9 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   5 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c          |  39 +++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 159 ++++++++++---
 drivers/gpu/drm/i915/i915_debugfs.c           |   4 +
 drivers/gpu/drm/i915/i915_drv.c               |   3 +
 drivers/gpu/drm/i915/i915_drv.h               |  12 +
 drivers/gpu/drm/i915/i915_irq.c               | 120 +++++++++-
 drivers/gpu/drm/i915/i915_pci.c               |  13 ++
 drivers/gpu/drm/i915/i915_reg.h               | 101 +++++++--
 drivers/gpu/drm/i915/intel_device_info.c      |   1 +
 drivers/gpu/drm/i915/intel_device_info.h      |   2 +
 drivers/gpu/drm/i915/intel_pch.c              |   6 +
 drivers/gpu/drm/i915/intel_pch.h              |   4 +
 drivers/gpu/drm/i915/intel_pm.c               |  17 +-
 drivers/gpu/drm/i915/intel_sideband.c         |  15 ++
 drivers/gpu/drm/i915/intel_sideband.h         |   2 +
 drivers/gpu/drm/i915/intel_uncore.c           |   4 +
 include/drm/i915_pciids.h                     |   4 +
 29 files changed, 1083 insertions(+), 123 deletions(-)

-- 
2.26.2

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             reply	other threads:[~2020-06-18  0:42 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-18  0:42 Lucas De Marchi [this message]
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Lucas De Marchi
2020-06-23 23:40   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 02/32] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI Lucas De Marchi
2020-06-23 23:56   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-06-24  0:13   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization Lucas De Marchi
2020-06-24  0:07   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 06/32] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-06-22  7:51   ` Daniel Vetter
2020-06-22  9:55     ` Jani Nikula
2020-06-23  4:54       ` Dave Airlie
2020-06-23  6:17         ` Daniel Vetter
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 08/32] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 09/32] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 10/32] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 11/32] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 12/32] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 13/32] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 14/32] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 15/32] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 16/32] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 17/32] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 18/32] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 19/32] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-06-22 18:35   ` Imre Deak
2020-06-22 20:43     ` Lucas De Marchi
2020-06-22 20:54       ` Imre Deak
2020-06-22 21:59         ` Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 21/32] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 22/32] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 23/32] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 24/32] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 25/32] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 26/32] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 27/32] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 28/32] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 29/32] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 30/32] drm/i915/dg1: Load DMC Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 31/32] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 32/32] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-06-18  0:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev2) Patchwork
2020-06-18  0:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-18  1:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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