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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, Vipin Anand <vipin.anand@intel.com>
Subject: [Intel-gfx] [v4 05/10] drm/i915/display: Enable HDR for Parade based lspcon
Date: Mon, 22 Jun 2020 18:30:24 +0530	[thread overview]
Message-ID: <20200622130029.28667-6-uma.shankar@intel.com> (raw)
In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com>

Enable HDR for LSPCON based on Parade along with MCA.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vipin Anand <vipin.anand@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 10e2823bf1ae..9034ce6f20b9 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -36,6 +36,7 @@
 #define LSPCON_VENDOR_MCA_OUI 0x0060AD
 
 #define DPCD_MCA_LSPCON_HDR_STATUS	0x70003
+#define DPCD_PARADE_LSPCON_HDR_STATUS	0x00511
 
 /* AUX addresses to write MCA AVI IF */
 #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
@@ -112,16 +113,20 @@ static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
 		container_of(lspcon, struct intel_digital_port, lspcon);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+	u32 lspcon_hdr_status_reg;
 	u8 hdr_caps;
 	int ret;
 
-	/* Enable HDR for MCA based LSPCON devices */
 	if (lspcon->vendor == LSPCON_VENDOR_MCA)
-		ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
-				       &hdr_caps, 1);
+		lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS;
+	else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
+		lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS;
 	else
 		return;
 
+	ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg,
+			       &hdr_caps, 1);
+
 	if (ret < 0) {
 		drm_dbg_kms(dev, "hdr capability detection failed\n");
 		lspcon->hdr_supported = false;
@@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
 
-	/*
-	 * Supporting HDR on MCA LSPCON
-	 * Todo: Add support for Parade later
-	 */
-	if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
-	    lspcon->vendor != LSPCON_VENDOR_MCA)
-		return;
-
 	switch (type) {
 	case HDMI_INFOFRAME_TYPE_AVI:
 		if (lspcon->vendor == LSPCON_VENDOR_MCA)
-- 
2.22.0

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  parent reply	other threads:[~2020-06-22 12:30 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-22 13:00 [Intel-gfx] [v4 00/10] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 01/10] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 02/10] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 03/10] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 04/10] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-06-22 13:00 ` Uma Shankar [this message]
2020-06-22 13:00 ` [Intel-gfx] [v4 06/10] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 07/10] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 08/10] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 09/10] drm/i915/lspcon: Do not send DRM " Uma Shankar
2020-06-22 13:00 ` [Intel-gfx] [v4 10/10] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-06-22 13:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev4) Patchwork
2020-06-22 13:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-22 16:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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