From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Subject: [PATCH 1/6] iommu/vt-d: Make Intel SVM code 64-bit only
Date: Tue, 23 Jun 2020 07:13:40 +0800 [thread overview]
Message-ID: <20200622231345.29722-2-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20200622231345.29722-1-baolu.lu@linux.intel.com>
Current Intel SVM is designed by setting the pgd_t of the processor page
table to FLPTR field of the PASID entry. The first level translation only
supports 4 and 5 level paging structures, hence it's infeasible for the
IOMMU to share a processor's page table when it's running in 32-bit mode.
Let's disable 32bit support for now and claim support only when all the
missing pieces are ready in the future.
Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode")
Suggested-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index b510f67dfa49..6dc49ed8377a 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -211,7 +211,7 @@ config INTEL_IOMMU_DEBUGFS
config INTEL_IOMMU_SVM
bool "Support for Shared Virtual Memory with Intel IOMMU"
- depends on INTEL_IOMMU && X86
+ depends on INTEL_IOMMU && X86_64
select PCI_PASID
select PCI_PRI
select MMU_NOTIFIER
--
2.17.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-06-22 23:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-22 23:13 [PATCH 0/6] [PULL REQUEST] iommu/vt-d: fixes for v5.8 Lu Baolu
2020-06-22 23:13 ` Lu Baolu [this message]
2020-06-22 23:13 ` [PATCH 2/6] iommu/vt-d: Set U/S bit in first level page table by default Lu Baolu
2020-06-22 23:13 ` [PATCH 3/6] iommu/vt-d: Don't apply gfx quirks to untrusted devices Lu Baolu
2020-06-22 23:13 ` [PATCH 4/6] iommu/vt-d: Enable PCI ACS for platform opt in hint Lu Baolu
2020-06-22 23:13 ` [PATCH 5/6] iommu/vt-d: Update scalable mode paging structure coherency Lu Baolu
2020-06-22 23:13 ` [PATCH 6/6] iommu/vt-d: Fix misuse of iommu_domain_identity_map() Lu Baolu
2020-06-23 8:12 ` [PATCH 0/6] [PULL REQUEST] iommu/vt-d: fixes for v5.8 Joerg Roedel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200622231345.29722-2-baolu.lu@linux.intel.com \
--to=baolu.lu@linux.intel.com \
--cc=iommu@lists.linux-foundation.org \
--cc=joro@8bytes.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.