From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 5/5] drm/i915/display: Implement WA 1408330847
Date: Thu, 25 Jun 2020 18:01:51 -0700 [thread overview]
Message-ID: <20200626010151.221388-5-jose.souza@intel.com> (raw)
In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com>
From the 3 WAs for PSR2 man track/selective fetch this is only one
needed when doing single full frames at every flip.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 078987a878b0..8755ab87740d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -553,13 +553,21 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_FAST_WAKE(7);
}
- if (dev_priv->psr.psr2_sel_fetch_enabled)
+ if (dev_priv->psr.psr2_sel_fetch_enabled) {
+ /* WA 1408330847 */
+ if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
+ intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+ DIS_RAM_BYPASS_PSR2_MAN_TRACK,
+ DIS_RAM_BYPASS_PSR2_MAN_TRACK);
+
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder),
PSR2_MAN_TRK_CTL_ENABLE);
- else if (HAS_PSR2_SEL_FETCH(dev_priv))
+ } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0);
+ }
/*
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
@@ -1099,6 +1107,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
psr_status_mask, 2000))
drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
+ /* WA 1408330847 */
+ if (dev_priv->psr.psr2_sel_fetch_enabled &&
+ (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
+ intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+ DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
+
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b6eb42b63db..4ab491426210 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7852,6 +7852,7 @@ enum {
# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
#define CHICKEN_PAR1_1 _MMIO(0x42080)
+#define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
#define DPA_MASK_VBLANK_SRD (1 << 15)
#define FORCE_ARB_IDLE_PLANES (1 << 14)
--
2.27.0
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next prev parent reply other threads:[~2020-06-26 1:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 1:01 [Intel-gfx] [PATCH v2 1/5] drm/i915: Add plane damage clips property José Roberto de Souza
2020-06-26 1:01 ` [Intel-gfx] [PATCH v2 2/5] drm/i915: Reorder intel_psr2_config_valid() José Roberto de Souza
2020-06-26 1:01 ` [Intel-gfx] [PATCH v2 3/5] drm/i915: Add PSR2 selective fetch registers José Roberto de Souza
2020-06-26 14:11 ` Mun, Gwan-gyeong
2020-06-29 19:41 ` Souza, Jose
2020-06-26 1:01 ` [Intel-gfx] [PATCH v2 4/5] drm/i915: Initial implementation of PSR2 selective fetch José Roberto de Souza
2020-06-30 15:33 ` Ville Syrjälä
2020-06-26 1:01 ` José Roberto de Souza [this message]
2020-06-27 8:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/5] drm/i915: Add plane damage clips property Patchwork
2020-06-27 9:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-30 17:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/5] drm/i915: Add plane damage clips property (rev2) Patchwork
2020-06-30 17:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-01 0:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-01 0:49 ` Souza, Jose
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