From: Krzysztof Kozlowski <krzk@kernel.org>
To: linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
Jisheng Zhang <Jisheng.Zhang@synaptics.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH] ARM: dts: berlin: Align L2 cache-controller nodename with dtschema
Date: Fri, 26 Jun 2020 10:06:41 +0200 [thread overview]
Message-ID: <20200626080642.4244-1-krzk@kernel.org> (raw)
Fix dtschema validator warnings like:
l2-cache-controller@ac0000: $nodename:0:
'l2-cache-controller@ac0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/berlin2.dtsi | 2 +-
arch/arm/boot/dts/berlin2cd.dtsi | 2 +-
arch/arm/boot/dts/berlin2q.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 3ab3cd250da7..6194857f8a02 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -106,7 +106,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 7cf3e6302d75..6f30d7eb3b41 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -71,7 +71,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index c44a32e873f4..b6a0acac6836 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -149,7 +149,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzk@kernel.org>
To: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>,
Jisheng Zhang <Jisheng.Zhang@synaptics.com>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: [PATCH] ARM: dts: berlin: Align L2 cache-controller nodename with dtschema
Date: Fri, 26 Jun 2020 10:06:41 +0200 [thread overview]
Message-ID: <20200626080642.4244-1-krzk@kernel.org> (raw)
Fix dtschema validator warnings like:
l2-cache-controller@ac0000: $nodename:0:
'l2-cache-controller@ac0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/berlin2.dtsi | 2 +-
arch/arm/boot/dts/berlin2cd.dtsi | 2 +-
arch/arm/boot/dts/berlin2q.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 3ab3cd250da7..6194857f8a02 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -106,7 +106,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 7cf3e6302d75..6f30d7eb3b41 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -71,7 +71,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index c44a32e873f4..b6a0acac6836 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -149,7 +149,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
--
2.17.1
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next reply other threads:[~2020-06-26 8:06 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 8:06 Krzysztof Kozlowski [this message]
2020-06-26 8:06 ` [PATCH] ARM: dts: berlin: Align L2 cache-controller nodename with dtschema Krzysztof Kozlowski
2020-07-28 6:36 ` Jisheng Zhang
2020-07-28 6:36 ` Jisheng Zhang
2020-07-28 7:33 ` Arnd Bergmann
2020-07-28 7:33 ` Arnd Bergmann
2020-07-28 7:42 ` Jisheng Zhang
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