From: Keqian Zhu <zhukeqian1@huawei.com>
To: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>,
Will Deacon <will@kernel.org>,
"Suzuki K Poulose" <suzuki.poulose@arm.com>,
Steven Price <steven.price@arm.com>,
"Sean Christopherson" <sean.j.christopherson@intel.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Mark Brown <broonie@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
Andrew Morton <akpm@linux-foundation.org>,
Alexios Zavras <alexios.zavras@intel.com>,
<liangpeng10@huawei.com>, <zhengxiang9@huawei.com>,
<wanghaibin.wang@huawei.com>, Keqian Zhu <zhukeqian1@huawei.com>
Subject: [PATCH v2 1/8] KVM: arm64: Set DBM bit for writable PTEs
Date: Thu, 2 Jul 2020 21:55:49 +0800 [thread overview]
Message-ID: <20200702135556.36896-2-zhukeqian1@huawei.com> (raw)
In-Reply-To: <20200702135556.36896-1-zhukeqian1@huawei.com>
DBM bit is used by MMU to differentiate a genuinely non-writable
page from a page that is only temporarily non-writable in order
to mark dirty.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
arch/arm64/include/asm/kvm_mmu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index b12bfc1f051a..2700442b0f75 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -169,6 +169,10 @@ void kvm_clear_hyp_idmap(void);
static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
{
pte_val(pte) |= PTE_S2_RDWR;
+
+ if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
+ pte_val(pte) |= PTE_DBM;
+
return pte;
}
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Keqian Zhu <zhukeqian1@huawei.com>
To: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Steven Price <steven.price@arm.com>,
liangpeng10@huawei.com, Alexios Zavras <alexios.zavras@intel.com>,
Mark Brown <broonie@kernel.org>, Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>,
Andrew Morton <akpm@linux-foundation.org>
Subject: [PATCH v2 1/8] KVM: arm64: Set DBM bit for writable PTEs
Date: Thu, 2 Jul 2020 21:55:49 +0800 [thread overview]
Message-ID: <20200702135556.36896-2-zhukeqian1@huawei.com> (raw)
In-Reply-To: <20200702135556.36896-1-zhukeqian1@huawei.com>
DBM bit is used by MMU to differentiate a genuinely non-writable
page from a page that is only temporarily non-writable in order
to mark dirty.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
arch/arm64/include/asm/kvm_mmu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index b12bfc1f051a..2700442b0f75 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -169,6 +169,10 @@ void kvm_clear_hyp_idmap(void);
static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
{
pte_val(pte) |= PTE_S2_RDWR;
+
+ if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
+ pte_val(pte) |= PTE_DBM;
+
return pte;
}
--
2.19.1
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Keqian Zhu <zhukeqian1@huawei.com>
To: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Keqian Zhu <zhukeqian1@huawei.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Steven Price <steven.price@arm.com>,
liangpeng10@huawei.com, Alexios Zavras <alexios.zavras@intel.com>,
zhengxiang9@huawei.com, Mark Brown <broonie@kernel.org>,
James Morse <james.morse@arm.com>, Marc Zyngier <maz@kernel.org>,
wanghaibin.wang@huawei.com, Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: [PATCH v2 1/8] KVM: arm64: Set DBM bit for writable PTEs
Date: Thu, 2 Jul 2020 21:55:49 +0800 [thread overview]
Message-ID: <20200702135556.36896-2-zhukeqian1@huawei.com> (raw)
In-Reply-To: <20200702135556.36896-1-zhukeqian1@huawei.com>
DBM bit is used by MMU to differentiate a genuinely non-writable
page from a page that is only temporarily non-writable in order
to mark dirty.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
arch/arm64/include/asm/kvm_mmu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index b12bfc1f051a..2700442b0f75 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -169,6 +169,10 @@ void kvm_clear_hyp_idmap(void);
static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
{
pte_val(pte) |= PTE_S2_RDWR;
+
+ if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
+ pte_val(pte) |= PTE_DBM;
+
return pte;
}
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-02 13:57 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 13:55 [PATCH v2 0/8] KVM: arm64: Support HW dirty log based on DBM Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu [this message]
2020-07-02 13:55 ` [PATCH v2 1/8] KVM: arm64: Set DBM bit for writable PTEs Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` [PATCH v2 2/8] KVM: arm64: Scan PTEs to sync dirty log Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` [PATCH v2 3/8] KVM: arm64: Modify stage2 young mechanism to support hw DBM Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` [PATCH v2 4/8] KVM: arm64: Save stage2 PTE dirty status if it is covered Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` [PATCH v2 5/8] KVM: arm64: Steply write protect page table by mask bit Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` [PATCH v2 6/8] KVM: arm64: Add KVM_CAP_ARM_HW_DIRTY_LOG capability Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-06 1:08 ` zhukeqian
2020-07-06 1:08 ` zhukeqian
2020-07-06 1:08 ` zhukeqian
2020-07-02 13:55 ` [PATCH v2 7/8] KVM: arm64: Sync dirty log parallel Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` [PATCH v2 8/8] KVM: Omit dirty log sync in log clear if initially all set Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-02 13:55 ` Keqian Zhu
2020-07-06 1:28 ` [PATCH v2 0/8] KVM: arm64: Support HW dirty log based on DBM zhukeqian
2020-07-06 7:54 ` Marc Zyngier
2020-07-13 2:47 ` zhukeqian
2020-07-13 14:53 ` Marc Zyngier
2020-07-28 2:11 ` zhukeqian
2020-07-28 7:52 ` Marc Zyngier
2020-07-28 8:32 ` zhukeqian
2021-01-06 6:55 ` Keqian Zhu
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